A processor includes a decode unit to decode a memory copy instruction that indicates a start of a source memory operand, a start of a destination memory operand, and an initial amount of data to be copied from the source memory operand to the destination memory operand. An execution unit, in response to the memory copy instruction, is to copy a first portion of data from the source memory operand to the destination memory operand before an interruption. A descending copy direction is to be used when the source and destination memory operands overlap. In response to the interruption, when the descending copy direction is used, the execution unit is to store a remaining amount of data to be copied, but is not to indicate a different start of the source memory operand, and is not to indicate a different start of the destination memory operand.