- 专利标题: Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architecture
-
申请号: US14883349申请日: 2015-10-14
-
公开(公告)号: US10073699B2公开(公告)日: 2018-09-11
- 发明人: Susan E. Eisen , Cliff Kucharski , Hung Q. Le , Dung Q. Nguyen , David R. Terry
- 申请人: International Business Machines Corporation
- 申请人地址: US NY Armonk
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY Armonk
- 代理机构: Patterson + Sheridan, LLP
- 主分类号: G06F9/38
- IPC分类号: G06F9/38 ; G06F9/30 ; G06F12/0875 ; G06F12/0891
摘要:
Method and system for writing a history buffer in a processing unit is provided. At least a first instruction and a second instruction are dispatched in a single processing cycle, targeting a same register file entry. The processing unit includes two or more processing slices, each processing slice comprising a corresponding history buffer and at least a portion of a register file. Upon determining that first result data corresponding to the first instruction is older than second result data corresponding to the second instruction, the first result data is written into a history buffer bypassing the register file entry, in response to the determination. Further, the second result data is written into the register file entry.
公开/授权文献
信息查询