The utility model relates to a data path assembly line. A data path assembly line that uses palingenetic logic block to improve the throughput of assembly line is described. In the embodiment, assembly line or its part include a plurality of parallel logical paths, and every logical path includes the same logic. Launch the input register level of every logical path initiating terminal in turn on continuous clock cycle to in turn with data read in every logical path and the operation of the ground of the logical out -phase on the different routes. With the output of the logical path one or more output register level of reading in, and use the multiplexer to merge the logical path, this multiplexer from the logical path one on any clock cycle selects output. Various optimization techniques have been described to can still use to deposit in various examples and think highly of regularly. In various examples, data path assembly line is in the treater.