The utility model discloses an output data refreshing, read-write and time sequence controller of a programmable logical controller (PLC). The output data refreshing, read-write and time sequence controller comprises a command and address control module, a 32-in 4-bit out memory, a 4-in 32-bit out memory, a data transmission control module, a PLC output image memory, a data latch and output port, and a pulse generator. The controller is applicable to design of a hard connection control circuit based on a field programmable gate array (FPGA); output data refreshing operation and data command read-write operation are automatically accomplished under the control of an internal time sequence pulse; when a data writing or reading command is executed, a WR signal is written into a command, and a soft element Y number and a Y group value are output; a second WRITE (WR) signal which is written into the command is written into data, the controller stores the data into the PLC output image memory one by one by using four bits as a group; a data reading command organizes the data by using the four bits as the group and sends a reading request signal; and a system sends READ (RD) signal reading data in response. The controller can automatically accomplish data reading and writing operation by fully utilizing FPGA parallel operation.