The present invention relates to a chip enable (CE) control circuit, a memory control circuit and a data processing system and provides a CE control circuit capable of reducing power consumption without degrading system performance. A CE control circuit generates a CE signal for controlling a state of a memory and sets the CE signal to valid (L level) when putting the memory into an enable state and sets the CE signal to invalid (H level) when putting the memory into a power saving state of low power consumption. In the case that a start request signal S_REQ is not received in a period when the CE signal is valid, the period when the CE signal is valid is extended to a period which corresponds to an expected value EV determined on the basis of an interval between the start request signal S_REQ and a RE signal and is longer than a CD signal holding time, and the CE signal is invalidated after this extended period. In the case that the start request signal S_REQ is received in the period when the CE signal is valid, the CE signal is kept validated.