The present invention is aimed at bonding a lower chip and an upper chip through bumps in a highly reliable manner, while ensuring a sufficient area for an external connection terminal region, by offsetting the upper chip to the lower chip. The substrate 2 has bumps 1 arranged on one surface thereof, and has a first chip 3 mounted on the other surface thereof. A second chip 4 is bonded to the first chip 3 through bumps 5, 6 while offsetting the second chip 4 to the first chip 3 in parallel. In the bonded state of the first chip 3 and the second chip 4, a part of the first chip 3 and a part ofthe second chip 4 are overlapped without aligning the centers of the both. The center of gravity of the second chip 4 falls inside a region surrounded by the outermost bumps between the first chip 3 and the second chip 4.