The process of forming stacked dielectric layer on semiconductor substrate with metal pattern includes the following steps: forming the first dielectric layer on the semiconductor substrate; forming the second dielectric layer over the first dielectric layer to constitute the composite dielectric layer. The second dielectric layer has greater dielectric constant, greater hardness and smaller thickness compared with the first dielectric layer. The stacked dielectric layer includes preferably 2 or 3 composite dielectric layer of the first dielectric layer and the second dielectric layer. Thesaid process of the present invention can avoid release of gases and cracking in the dielectric layer and can meet the requirement of reducing capacitance between the interconnection wires.