Provided in the embodiments of the present invention are an asynchronous FIFO circuit and a time delay determination method, which relate to the field of wireless communication. The asynchronous FIFOcircuit comprises: a write clock generating circuit, a read clock generating circuit, a write address generating circuit, a read address generating circuit, a random access memory, a delay line circuit, a synchronous logic circuit, an address comparing logic circuit and a processor; the second output terminal of the write address generating circuit is connected to the first input terminal of the delay line circuit, the second input terminal of the delay line circuit is connected to the first output terminal of the processor, the output terminal of the delay line circuit is connected to the first input terminal of the synchronous logic circuit, the output terminal of the synchronous logic circuit is connected to the first input terminal of the address comparing logic circuit, the output terminal of the read address generating circuit is connected to the third input terminal of the address comparing logic circuit, and the first output terminal of the address comparing logic circuit is connected to the input terminal of the processor. The present invention can accurately determine the time delay of the asynchronous FIFO circuit.