A data processing system comprises a processor to perform operations specified by program instructions including at least one vector processing program instruction supporting processing of up to Nmax vector elements associated with respective vector processing lanes. The system comprises an instruction decoder to decode the program instructions and generate signals to control the processor to perform said operations. The instruction decoder comprises predicated-loop instruction decoder circuitry to decode a predicated-loop instruction having associated therewith a number of vector elements Nve to be processed during a number of iterations of a program loop body to be performed. The processor comprises predication loop control circuitry to operate when Nve/Nmax does not equal a whole number at least partially to suppress processing in one or more of said vector processing lanes during one or more iterations such that a total number of vector elements processed during the iterations is Nve. Nmax can be a constant value independent of the program instruction within the loop body, and can be given by the whole number portion of VRwidth/VEwidth, where VRwidth is the number of bits of the vector registers of the processor, and VEwidth is the number of bits of the vector elements.