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发明授权
CN107293538B 暂态电压抑制集成电路 有权

暂态电压抑制集成电路
摘要：
本发明提供一种暂态电压抑制集成电路，包括输入输出引脚、接地引脚、基板、第一暂态电压抑制晶粒以及第二暂态电压抑制晶粒。基板提供共同总线。第一暂态电压抑制晶粒配置在基板上，且包括第一输入输出端与第一参考接地端。第二暂态电压抑制晶粒配置在基板上，且包括第二输入输出端与第二参考接地端。第二参考接地端通过共同总线电性连接至第一参考接地端，第一输入输出端连接输入输出引脚，第二输入输出端连接接地引脚。
摘要（英）：

A transient voltage suppressing (TVS) integrated circuit includes an input output pin, a ground pin, a substrate, a first TVS die and a second TVS die. The substrate provides a common bus. The first TVS die is disposed on the substrate, and includes a first input output terminal and a first reference ground terminal. The second TVS die is disposed on the substrate and includes a second input output terminal and a second reference ground terminal. The second reference ground terminal is electrically coupled to the first reference ground terminal through the common bus, and the first input output terminal is coupled to the first input out pin, and the second input output terminal is coupled to a ground pin.

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