The invention discloses a wafer level chip scale package (WLCSP) structure with a through-silicon via continuous state and a manufacturing method thereof. The WLCSP structure mainly comprises a device chip, a carrier chip laminated on the device chip, a protective cover, and a through-silicon via structure. A metal interlinked parallel pad combination is embedded in the device chip. An offset pad is arranged on the device chip and is connected to the metal interlinked parallel pad combination. A partition conductor lug is arranged on the offset pad. A partition adhesive layer is formed on the device chip and covers the partition conductor lug. The protective cover is pressed on the partition adhesive layer. The through-silicon via structure comprises a through hole and a porous metal layer. The through hole is slightly-eccentrically aligned to the offset pad and penetrates the carrier chip and the device chip continuously. The porous metal layer is formed in the through hole and is connected to the offset pad. The through hole is non-centrally aligned to the partition conductor lug. A protective layer is formed on the carrier chip and covers the through hole. The conductor lug is partitioned by the offset pad so as to ensure the continuous state of the through-silicon via structure.