A memory circuit characterized by comprising a plurality of cells and a control unit, as follows. The plurality of cells are laid out in a plurality of rows and a plurality of columns so as to form a plurality of banks obtained by partitioning the plurality of rows. Each bank contains one or more rows. Each cell comprises the following: a bistable circuit that holds data; and a nonvolatile element that stores, in a nonvolatile manner, the data held in the bistable circuit and restores said data to the bistable circuit. The control unit: performs a store operation on each row in turn; sets, to a first voltage, the voltage supplied to a power supply for the cells in a first bank that is one of the abovementioned banks and includes the row on which the aforementioned store operation is being performed; and sets, to a second voltage that is lower than the aforementioned first voltage but at which the data in the bistable circuits is preserved, the voltages supplied to power supplies for cells that are not in the aforementioned first bank.