Provided is a unit shift register circuit which constitutes each stage of a shift register circuit, and which includes: an output transistor (T1) in which a predetermined clock signal is input to the drain terminal, and which outputs an output signal (OUT) from the source terminal; and a setting transistor (T2), wherein the transistor (T2) is connected at the source terminal thereof to one gate electrode of the output transistor (T1), an input signal (S) is input to the drain terminal, and an input signal (VS) of higher voltage than the voltage of the input signal (S) is input to the gate electrode during charging of the gate electrode (node (VC)) of the output transistor (T1).