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发明授权
CN105226059B 紧凑CMOS器件绝缘结构 有权 转让

紧凑CMOS器件绝缘结构
摘要：
一种集成电路包括一个第一导电类型的第一阱，形成在半导体层中，第一阱罩住有源器件，并且连接到第一阱电势，一个第二导电类型的第二阱，形成在半导体层中，包围着第一阱，第二阱罩住有源器件，并且连接到第二阱电势，一个第二导电类型的掩埋层，形成在第一阱下方，并且部分重叠包围着第一阱的第二阱。在一个可选实施例中，集成电路包括一个第二导电类型的第三阱，取代掩埋层，第三阱含有第一阱，并且部分衬底包围着第一阱的第二阱。
摘要（英）：

An integrated circuit includes a first well of the first conductivity type formed in a semiconductor layer where the first well housing active devices and being connected to a first well potential, a second well of a second conductivity type formed in the semiconductor layer and encircling the first well where the second well housing active devices and being connected to a second well potential, and a buried layer of the second conductivity type formed under the first well and overlapping at least partially the second well encircling the first well. In an alternate embodiment, instead of the buried layer, the integrated circuit includes a third well of the second conductivity type formed in the semiconductor layer where the third well contains the first well and overlaps at least partially the second well encircling the first well.

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