The present invention relates to the field of data processing, and discloses a high-speed parallel processing architecture for a data center. The high-speed parallel processing architecture comprises a plurality of processing boards, and is characterized in that each processing board comprises at least two transceivers, at least one FPGA programmable logic chip and at least two processors (CPUs), wherein the CPUs are connected with with the FPGA chip through CPU high-speed serial interfaces; and a plurality of high-speed serial transceiver cores and a plurality of corresponding coprocessors (MCUs) are arranged in the FPGA chip; a plurality of embedded memories corresponding to each coprocessor MCU are embedded into the FPGA ; and each embedded memory is configured to be in a dual-port mode capable of reading and writing. According to the high-speed parallel processing architecture, an embedded CPU+FPGA architecture is realized; high-speed parallel hardware algorithms are realized, so that processing ability of basic computing elements is greatly improved, and system schedule delay is reduced.