A sensing circuit for a nanometer flash memory device comprises: a memory data read block coupled to a selected flash memory cell and comprising a bit line, a first parasitic capacitor from a first adjacent bit line and a second parasitic capacitor from a second adjacent bit line; a memory reference read block coupled to a reference memory cell; and a differential amplifier block coupled to the memory data read block and the memory reference read block for determining a value stored in the selected flash memory cell. Each of the memory data read block and the memory reference read block comprises a current source, a cascoding sensing NMOS transistor, a bitline clamp NMOS transistor, a diode connected sensing load PMOS transistor, and a capacitor. The memory data read block and memory reference read block are coupled to a precharge circuit to compensate for the first parasitic capacitor and the second parasitic capacitor.