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Invention Grant
CN104520838B 用于多核处理器的可调谐多层次STT-MRAM高速缓存 有权

用于多核处理器的可调谐多层次STT-MRAM高速缓存
Abstract:
给出了一种多核处理器。该多核处理器包括与该多核处理器的第一核相关联并且根据第一属性来调谐的第一自旋转移矩磁阻随机存取存储器(STT‑MRAM)高速缓存、以及与该多核处理器的第二核相关联并且根据第二属性来调谐的第二STT‑MRAM高速缓存。
Abstract(English):

A multi-core processor is presented. The multi-core processor includes a first spin transfer torque magnetoresistive random-access memory (STT-MRAM) cache associated with a first core of the multi-core processor and tuned according to first attributes and a second STT-MRAM cache associated with a second core of the multi-core processor and tuned according to second attributes.

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