The invention relates to a memory architecture for turbo decoder. Disclosed are various embodiments that provide turbo decoding implemented as at least a portion of baseband processing circuitry. An input bit stream may be divided into a set of code blocks and a first code block may be separated from the set of code blocks. A hybrid automatic repeat request (HARQ) process is performed on the first code block to generate a processed first code block. The processed first code block is stored in an incremental redundancy (IR) buffer. A turbo decoding process is performed on the processed first code block to generate decoded first code block data and the decoded first code block data is stored in an external memory. The processed first code block is removed from the IR buffer for decoding a remaining portion of the set of code blocks.