To provide two clock signals (CLK1, CLK2) of slightly different frequencies (f1, f2) with defined time or phase delay, the first clock signal (CLK1) is generated at the first clock frequency (f1), the first clock frequency (f1) is divided by a first integer (K1) to produce a first auxiliary signal (CLK11), the second clock signal (CLK2) is divided by a second integer (K2) to produce a second auxiliary signal (CLK21), an error signal (ERR) is generated by individually weighting and comparing the cycle durations or phasing of the first and second auxiliary signals (CLK11, CLK21), and said second clock signal (CLK2) is generated by means of a voltage-controlled oscillator (17) controlled by said error signal (ERR).