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发明授权
CN102543159B 一种DDR控制器及其实现方法和芯片 有权

一种DDR控制器及其实现方法和芯片
摘要：
本发明适用于DDR控制器技术领域，提供了一种DDR控制器及其实现方法和芯片，所述方法包括下述步骤：同时解析缓存的多个命令，预判所述解析的每一命令访问的地址的Bank和Row与当前正在执行的命令的地址Bank和Row的关系，将PRECHARGE命令和ACTIVE命令提前发送。本发明通过同时解析缓存的多个命令，并预判上述解析的每一命令访问的地址的Bank和Row与当前正在执行的命令的地址Bank和Row的关系，将PRECHARGE命令和ACTIVE命令提前发送，使得原来串行发送的PRECHARGE命令和ACTIVE命令可以提前以并行的掩蔽在READ或者WRITE等期间，充分利用了DDR器件的带宽。
摘要（英）：

Provided are a DDR controller and a method and chip for implementing same, which are suitable to be used in the field of DDR controller technology. The method comprises the following the steps: analysing a plurality of cached commands at the same time (S501); prejudging the relationship between the Bank and Row of an address accessed by each analysed command and the Bank and Row of an address of a command being executed; and sending a PRECHARGE command and an ACTIVE command in advance. According to the above technical solution, the pre-charge command and active command which were formerly sent in series can be carried out in advance so as to be concealed in parallel during the READ, or WRITE, etc. period, making the best use of the bandwidth of the DDR device.

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