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发明公开
CN102543159A 一种DDR控制器及其实现方法和芯片 有权

一种DDR控制器及其实现方法和芯片
摘要：
本发明适用于DDR控制器技术领域，提供了一种DDR控制器及其实现方法和芯片，所述方法包括下述步骤：同时解析缓存的多个命令，预判所述解析的每一命令访问的地址的Bank和Row与当前正在执行的命令的地址Bank和Row的关系，将PRECHARGE命令和ACTIVE命令提前发送。本发明通过同时解析缓存的多个命令，并预判上述解析的每一命令访问的地址的Bank和Row与当前正在执行的命令的地址Bank和Row的关系，将PRECHARGE命令和ACTIVE命令提前发送，使得原来串行发送的PRECHARGE命令和ACTIVE命令可以提前以并行的掩蔽在READ或者WRITE等期间，充分利用了DDR器件的带宽。
摘要（英）：

The invention provides a double data rate (DDR) controller and a realization method thereof, and a chip, which are suitable for the technical field of DDR controllers. The method comprises the following steps of: analyzing a plurality of cached commands simultaneously; prejudging the relation between addresses Bank and Row which are accessed by each analyzed command and addresses Bank and Row of the command which is performed at present; and transmitting a PRECHARGE command and an ACTIVE command in advance. According to the method, the cached commands are analyzed simultaneously, the relation between the addresses Bank and Row which are accessed by each analyzed command and the addresses Bank and Row of the command which is performed at present is prejudged, and the PRECHARGE command and the ACTIVE command are transmitted in advance, so that the PRECHARGE command and the ACTIVE command which are serially transmitted originally can be concurrently concealed in periods of READ or WRTTE and the like in advance, and the bandwidth of a DDR device is fully utilized.

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