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发明授权
CN101556927B 一种芯片封装工艺中的打线方法 失效 - 权利终止

一种芯片封装工艺中的打线方法
摘要：
本发明揭露了一种芯片封装工艺中的打线方法，用于将焊线连接于芯片的打线焊垫与承载芯片的承载件的引脚之间，其包括如下步骤：(1)将焊料点于芯片承载件的一承载单元上；(2)将芯片置于上述点有焊料的承载单元上；(3)旋转并压焊上述芯片，使得上述芯片上的打线焊垫相对于上述承载件的引脚倾斜；(4)打线于上述旋转后的芯片的打线焊垫与承载件的引脚之上。可见，该方法从现有机台的特点出发，打破了常规的粘片模式，将芯片旋转压焊于承载单元上，而于打线时相对增大了打线焊垫的打线面积或拉长了打线焊垫与承载件引脚之间的距离，利于焊线的正常焊接，而降低了开/短路测试废品与错焊废品的出现率。
摘要（英）：

The invention discloses a wire bonding method in a chip package process, which is used for connecting a bonding wire between a wire bonding pad of a chip and a pin of a bearing part of a bearing chip.The method comprises the steps as follows: (1) dotting a solder on a bearing unit of the bearing part; (2) placing the chip on the bearing unit with the solder; (3) rotating and bonding the chip so that the wire bonding pad on the chip is inclined relative to the pin of the bearing part; and (4) bonding a wire on the wire bonding pad of the rotated chip and the pin of the bearing part, therefore,based on the characteristic of the prior machine, the method breaks through the conventional mode of an adhesive tape, rotates and bonds the chip on the bearing unit to relatively increase the wire bonding area of the wire bonding pad or increase the distance between the wire bonding pad and the pin of the bearing part, thereby the bonding wire is welded normally and the occurrence rate of open/short circuit testing waste products and wrongly welded waste products is reduced.

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