The invention is used to solve the competitive interest between a high-speed storage access and a low-power performance. A data processing system(20) has a high performance chip election(HPCE) signal, the chip election signal is programmable in function, which is cognizanced according to an access dutyfactor in a bus period with scheduled number. The bit of an option register allows the users to HPCE program to the cognizance for maintaining in the following ways: always, never, or many periods after the last effective addresses match, which allows the users to determine a compromise between the high-speed storage access and the low-power performance. The data processing system provides a programmable chip election signal non-value in a bus period before finishing the transaction processing, and provides extra time to the external device to disconnect from the current bus period before the beginning of the next bus period. The data processing device has a pulse bunch address generator(BAG)(55) with a programmable transaction processing mode which can be used in the cache and a prefetching structured type at one time.