The invention relates to a layout design device, comprising a memory device for storing the circuit data of a circuit consisting of a plurality of transistors; a search device for searching for a set of routes formed so that passage through any one of the transistors occurs only one time and so that the combination of routes in one set can cover the entire circuit network; an extraction device for extracting a set of routes having the smallest number of routes in sets of route found by searching; a width determination device for determining the layout width according to the widths of source and drain electrodes of each transistor, the width of the region between the source and drain electrodes, the width of the region between some of the adjacent pairs of the transistors not combined intoa common electrode, the number of transistors, and the smallest number of routes; and a layout determination device for forming information about the layout, wherein, all the source, drain and gate electrodes of the transistor included in the circuit are placed in a small-width region whose width is determined according to the width of the layout; and an output device for outputting the layout information determined by the layout determination device.