A memory utilizing programmable delay circuits to control address buffers is disclosed. A programmable delay circuit is provided for each block of the memory device. Each of the delays within each block is programmed by a global fuse circuit. After fabrication of the memory device onto an integrated circuit (IC), all of the data paths within each block are measured under various voltage and temperature conditions to identify the slowest data path of all blocks of the memory device. The global fuse circuit used to program the delay device within each of the blocks is also used to program the delay device within the clock control circuit so that the program delay within the clock control circuit and the data blocks are essentially the same.