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公开(公告)号：US20240266369A1
公开(公告)日：2024-08-08
申请号：US18437410
申请日：2024-02-09
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Atsushi UMEZAKI
IPC: H01L27/12 , G09G3/14 , G09G3/32 , G09G3/36 , G11C19/00 , H01L29/786 , H03B1/00 , H03K3/00 , H03K17/687
CPC classification number: H01L27/1255 , G09G3/14 , G09G3/32 , G09G3/36 , G11C19/00 , H01L29/7869 , H03B1/00 , H03K3/00 , H03K17/6871 , G09G2300/0426 , G09G2310/0286 , G09G2330/021
Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.
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公开(公告)号：US12034441B2
公开(公告)日：2024-07-09
申请号：US18165195
申请日：2023-02-06
Applicant: Kioxia Corporation
Inventor： Yasuhiro Hirashima , Masaru Koyanagi , Yutaka Takayama
IPC: G11C7/10 , H01L23/538 , H03K3/00 , H03K19/0175
CPC classification number: H03K19/017509 , H01L23/5384
Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.
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公开(公告)号：US11990910B2
公开(公告)日：2024-05-21
申请号：US17729844
申请日：2022-04-26
Applicant: Nordic Semiconductor ASA
Inventor： Harald Garvik
Abstract: A circuit portion comprises a load circuit portion and a bias circuit portion. The load circuit portion comprises a load transistor. The bias circuit portion comprises a replica transistor matched to the load transistor and connected to the load transistor at a node such that when a current flows through the replica transistor, a current proportional to the current through the replica transistor flows through the load transistor. The bias circuit portion also comprises a current input for receiving an input current, a supply voltage input for receiving a supply voltage, and a feedback loop arranged to: adjust a voltage at the node connecting the replica transistor and the load transistor such that the replica transistor conducts a current proportional to the input current, and counteract variations in the voltage at the node connecting the replica transistor and the load transistor arising from changes in the supply voltage.
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公开(公告)号：US11979158B2
公开(公告)日：2024-05-07
申请号：US17825704
申请日：2022-05-26
Inventor： Cheng-Yu Lin , Yung-Chen Chien , Jia-Hong Gao , Jerry Chang Jui Kao , Hui-Zhong Zhuang
IPC: H03K3/00 , H03K3/012 , H03K3/037 , H03K3/356 , H03K3/3562
CPC classification number: H03K3/35625 , H03K3/012 , H03K3/0372 , H03K3/356104
Abstract: An integrated circuit (IC) device includes a master latch circuit having a first clock input and a data output, a slave latch circuit having a second clock input and a data input electrically coupled to the data output of the master latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input by a first electrical connection configured to have a first time delay between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input by a second electrical connection configured to have a second time delay between the clock circuit and the second clock input. The first time delay is longer than the second time delay.
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公开(公告)号：US11955961B2
公开(公告)日：2024-04-09
申请号：US17879047
申请日：2022-08-02
Inventor： Hong Gu Ji , Dong Min Kang , Byoung-Gue Min , Jongmin Lee , Kyu Jun Cho
IPC: H03K3/00 , H03K17/687 , H03K17/693
CPC classification number: H03K17/687
Abstract: Disclosed is a switch circuit for an ultra-high frequency band, which includes a transistor including a first terminal connected to an input stage, a second terminal connected to an output stage, and a gate terminal, an inductor connected to the transistor in parallel, between the input stage and the output stage, a variable gate driver to apply a gate input voltage to the gate terminal and, an input resistor connected between the variable gate driver and the gate terminal. The variable gate driver adjusts the gate input voltage to be in one of a first voltage level for turning on the transistor and a second voltage level for turning off the transistor. The second voltage level varies depending on a capacitance between the first terminal and the second terminal, when the transistor is in a turn-off state.
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公开(公告)号：US11888332B2
公开(公告)日：2024-01-30
申请号：US17820538
申请日：2022-08-17
Applicant: Navitas Semiconductor Limited
Inventor： Daniel M. Kinzer , Santosh Sharma , Ju Jason Zhang
IPC: H02M3/158 , H03K3/00 , H03K17/10 , H02J7/00 , H01L23/495 , H01L27/02 , H01L23/62 , H02M1/088 , H03K3/012 , H01L29/20 , H03K19/0185 , H01L25/07 , H02M3/157 , H03K3/356 , H01L27/088 , H01L23/528 , H01L29/10 , H01L29/40 , H01L29/417 , H02M1/00 , H02M3/155
CPC classification number: H02J7/00 , H01L23/49503 , H01L23/49562 , H01L23/49575 , H01L23/528 , H01L23/62 , H01L25/072 , H01L27/0248 , H01L27/088 , H01L27/0883 , H01L29/1033 , H01L29/2003 , H01L29/402 , H01L29/41758 , H02M1/088 , H02M3/157 , H02M3/1584 , H02M3/1588 , H03K3/012 , H03K3/356017 , H03K17/102 , H03K19/018507 , H01L2924/00 , H01L2924/0002 , H02M1/0048 , H02M3/155 , Y02B40/00 , Y02B70/10 , H01L2924/0002 , H01L2924/00
Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.
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公开(公告)号：US11881859B2
公开(公告)日：2024-01-23
申请号：US17749278
申请日：2022-05-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abhishek Gupta , Sayantan Gupta
IPC: H03K3/00 , H03K3/3565 , H03K3/2893
CPC classification number: H03K3/3565 , H03K3/2893
Abstract: A circuit includes an inverter coupled between an input and an output. The inverter includes first and second pull-down transistors having control terminals coupled to the input, a pull-up resistor, and a pull-up transistor having a control terminal coupled to the input. The first and second pull-down transistors are coupled in series along a pull-down path extending between a first voltage supply terminal and the output. The pull-up resistor and pull-up transistor are coupled in series along a pull-up path extending between a second voltage supply terminal and the output. A hysteresis transistor has a control terminal coupled to the output. The hysteresis transistor is coupled to the inverter along a hysteresis path extending between the first voltage supply terminal and the pull-up path. A clamp circuit is coupled to the inverter along a clamp path extending between the first voltage supply terminal and the pull-down path.
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公开(公告)号：US11863189B2
公开(公告)日：2024-01-02
申请号：US17338107
申请日：2021-06-03
Inventor： Yu-Kai Tsai , Chia-Hui Chen , Chia-Jung Chang
IPC: H03K3/00 , H03K3/037 , H03K3/13 , H03K3/3565
CPC classification number: H03K3/0377 , H03K3/13 , H03K3/3565
Abstract: An integrated circuit includes an upper threshold circuit, a lower threshold circuit, and a control circuit. The upper threshold circuit is configured to set a logic level of a first enabling signal based on comparing an input voltage signal with an upper threshold voltage. The lower threshold circuit is configured to set a logic level of a second enabling signal based on comparing the input voltage signal with a lower threshold voltage. The control circuit is configured to change an output voltage signal from a first voltage level to a second voltage level when the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively.
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公开(公告)号：US11831315B1
公开(公告)日：2023-11-28
申请号：US17875608
申请日：2022-07-28
Applicant: Cadence Design Systems, Inc.
Inventor： Sambasiva Rao Udatha , Uma Suri Appa Rao Kandregula
Abstract: High-speed signal propagation circuits are biased by a temperature-compensating signal-swing calibrator to yield a target output signal amplitude across process, voltage and temperature corners, avoiding the power-consumptive over-biasing conventionally employed to avoid under-amplitude conditions in slow-process, low-voltage and/or high temperature conditions.
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公开(公告)号：US11791807B2
公开(公告)日：2023-10-17
申请号：US17676005
申请日：2022-02-18
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Marco Viti
Abstract: A multi-level pulser circuit comprises a set of first input pins for receiving respective positive voltage signals at different voltage levels, a set of second input pins for receiving respective negative voltage signals at different voltage levels, and a reference input pin configured to receive a reference voltage signal intermediate the positive voltage signals and the negative voltage signals. The circuit comprises an output pin configured to supply a pulsed output signal. The circuit further comprises control circuitry configured to selectively couple the output pin to one of the first input pins, the second input pins and the reference input pin to generate the pulsed output signal at the output pin. The control circuitry is further configured to selectively couple at least one of the second input pins and the reference input pin to the output pin during falling transitions of the pulsed output signal between two positive voltage levels, and selectively couple at least one of the first input pins and the reference input pin to the output pin during rising transitions of the pulsed output signal between two negative voltage levels.
