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公开(公告)号：US11296861B1
公开(公告)日：2022-04-05
申请号：US17514752
申请日：2021-10-29
发明人： Long Zhang , Wei Wang , Shuihai Hu
摘要： A Paillier decryption system, IC, and method. The IC includes: a modular exponentiation module, for performing modular exponentiation operations related to a first subitem and a second subitem, where a Paillier decryption process of encrypted data is divided into a first subitem and a second subitem according to the Chinese remainder theorem, the first subitem corresponding to a first prime, the second subitem corresponding to a second prime, a public key of the encrypted data being a product of the first prime and the second prime, a bit width of the first prime being the same as a bit width of the second prime; a first module combination corresponding to the first subitem, for determining a computation result of the first subitem; and a second module combination corresponding to the second subitem, for determining a computation result of the second subitem.
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2.发明申请公开(公告)号：US20230088897A1
公开(公告)日：2023-03-23
申请号：US17888024
申请日：2022-08-15
摘要： A heterogeneous processing system for federated learning and privacy-preserving computation, including: a serial subsystem configured for distributing processing tasks and configuration information of processing tasks, the processing task indicating performing an operation corresponding to computing mode on one or more operands; and a parallel subsystem configured for, based on the configuration information, selectively obtaining at least one operand of the one or more operands from an intermediate result section on the parallel subsystem while obtaining remaining operand(s) of the one or more operands with respect to the at least one operand from the serial subsystem, and performing the operation on the operands obtained based on the configuration information.
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公开(公告)号：US11521129B2
公开(公告)日：2022-12-06
申请号：US17514669
申请日：2021-10-29
发明人： Long Zhang , Wei Wang , Shuihai Hu
摘要： A processing device for federated learning, including: a modular exponentiation module including at least one modular exponentiation engine; a pre-processing module for providing operations corresponding to a plurality of operator modes; a montgomerization module for providing montgomerization operations; a confusion calculation module for providing modular multiplication operations in montgomery space; a montgomery reduction module for providing montgomery reduction operations; and a controller for determining, according to an input operator mode, whether to enable at least two modules out of the pre-processing module, the montgomerization module, the confusion calculation module, and the montgomery reduction module, so as for cooperatively performing the input operator mode together with the modular exponentiation module.
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4.发明授权公开(公告)号：US11676074B2
公开(公告)日：2023-06-13
申请号：US17888024
申请日：2022-08-15
CPC分类号： G06N20/00 , G06F9/4881 , H04L9/008
摘要： A heterogeneous processing system for federated learning and privacy-preserving computation, including: a serial subsystem configured for distributing processing tasks and configuration information of processing tasks, the processing task indicating performing an operation corresponding to computing mode on one or more operands; and a parallel subsystem configured for, based on the configuration information, selectively obtaining at least one operand of the one or more operands from an intermediate result section on the parallel subsystem while obtaining remaining operand(s) of the one or more operands with respect to the at least one operand from the serial subsystem, and performing the operation on the operands obtained based on the configuration information.
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公开(公告)号：US20220147873A1
公开(公告)日：2022-05-12
申请号：US17514669
申请日：2021-10-29
发明人： Long ZHANG , Wei WANG , Shuihai HU
摘要： A processing device for federated learning, including: a modular exponentiation module including at least one modular exponentiation engine; a pre-processing module for providing operations corresponding to a plurality of operator modes; a montgomerization module for providing montgomerization operations; a confusion calculation module for providing modular multiplication operations in montgomery space; a montgomery reduction module for providing montgomery reduction operations; and a controller for determining, according to an input operator mode, whether to enable at least two modules out of the pre-processing module, the montgomerization module, the confusion calculation module, and the montgomery reduction module, so as for cooperatively performing the input operator mode together with the modular exponentiation module.
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