公开(公告)号：US20240222191A1

公开(公告)日：2024-07-04

申请号：US18089773

申请日：2022-12-28

Applicant: Winbond Electronics Corp.

Inventor： Ping-Lung YU ,  Po-Chun SHAO ,  Chu-Chun HSIEH

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76859 ,  H01L21/76846 ,  H01L21/76883 ,  H01L23/53266

Abstract: A method for forming a semiconductor structure includes providing a substrate with an opening in or on the substrate. The method further includes conformally forming a barrier layer in the opening and on the substrate and performing an implantation process to implant a dopant into the barrier layer. The method further includes conformally forming a capping layer on the barrier layer and performing an annealing process, such that the dopant diffuses into the grain boundary of the barrier layer. The method further includes removing the capping layer and filling the opening with a conductive material.

公开(公告)号：US20250070068A1

公开(公告)日：2025-02-27

申请号：US18485574

申请日：2023-10-12

Applicant: Winbond Electronics Corp.

Inventor： Po-Chun SHAO ,  Ping-Lung YU

IPC: H01L23/00

Abstract: A semiconductor structure includes a semiconductor substrate, an insulating layer, a conductive feature and an anisotropic conductive structure. The insulating layer is disposed above the semiconductor substrate. The conductive feature is disposed in the insulating layer, wherein a top surface of the conductive feature is adjacent to a top surface of the insulating layer. The anisotropic conductive structure is disposed on the insulating layer and the conductive feature. The anisotropic conductive structure includes a metal oxide porous layer and conductive pillars. The metal oxide porous layer has a first nano-through-hole array exposing the top surface of the conductive feature and a second nano-through-hole array exposing the top surface of the insulating layer. The conductive pillars fill the first nano-through-hole array, wherein the conductive pillars are in contact with the top surface of the conductive feature.

公开(公告)号：US20230230835A1

公开(公告)日：2023-07-20

申请号：US17901525

申请日：2022-09-01

Applicant: Winbond Electronics Corp.

Inventor： Po-Chun SHAO ,  Shih-Hsien CHEN ,  Ping-Lung YU

IPC: H01L21/033 ,  H01L29/788 ,  H01L29/417 ,  H01L21/3115 ,  H01L21/3213

CPC classification number: H01L21/0337 ,  H01L21/31155 ,  H01L21/32139 ,  H01L29/788 ,  H01L29/41725

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a target layer on the substrate, and a hard mask layer doped with a group IV-A element on the target layer. The number of sp3 orbital bonds in the hard mask layer is greater than the number of sp2 orbital bonds.

公开(公告)号：US20220102546A1

公开(公告)日：2022-03-31

申请号：US17037432

申请日：2020-09-29

Applicant: Winbond Electronics Corp.

Inventor： Ping-Lung YU ,  Po-Chun SHAO

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/66

Abstract: A non-volatile memory structure includes a substrate, a tunnel dielectric layer on the substrate, and several separate gate structures on the substrate. The gate structures are disposed within an array region of the substrate. Each gate structure includes a floating gate and a control gate on the floating gate. A first dielectric layer is formed above the substrate and covers the top surface of the tunnel dielectric layer. The first dielectric layer also covers the side surfaces and the top surface of each gate structure. Gaps between portions of the first dielectric layer on the side surfaces of two adjacent gate structures are fully filled with the air to form air gaps. Several insulating blocks are formed on the first dielectric layer, and they correspond to the gate structures. A second dielectric layer is formed on the insulating blocks and covers the insulating blocks and the air gaps.