公开(公告)号：US20230326980A1

公开(公告)日：2023-10-12

申请号：US17737041

申请日：2022-05-05

Applicant: United Microelectronics Corp.

Inventor： Chi-Hsiao Chen ,  Tzyy-Ming Cheng ,  Wei Jen Chen ,  Kai Lin Lee

IPC: H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/778

CPC classification number: H01L29/402 ,  H01L29/7786 ,  H01L29/42316 ,  H01L29/41775

Abstract: A high electron mobility transistor (HEMT) device including the following components is provided. A gate electrode is located on a barrier layer. A source electrode is located on the first side of the gate electrode. A drain electrode is located on the second side of the gate. A source field plate is connected to the source electrode. The source field plate includes first, second, and third field plate portions. The first field plate portion is connected to the source electrode and is located on the first side of the gate electrode. The second field plate portion is located on the second side of the gate electrode. The third field plate portion is connected to the end of the first field plate portion and the end of the second field plate portion. The source field plate has a first opening located directly above the gate electrode.

公开(公告)号：US08823109B2

公开(公告)日：2014-09-02

申请号：US13736951

申请日：2013-01-09

Applicant: United Microelectronics Corp.

Inventor： Wen-Han Hung ,  Tsai-Fu Chen ,  Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the silicon cap layer, and covering only a portion of the silicon cap layer.

Abstract translation: 在本发明中提供一种晶体管结构。 晶体管结构包括：包括N型阱的衬底，设置在N型阱上的栅极，设置在栅极上的间隔物，位于衬垫下方的衬底中的第一轻掺杂区域，P型源极/漏极 位于栅极两侧的衬底中的覆盖P型源/漏区和第一轻掺杂区的硅帽层和设置在硅帽层上的硅化物层，并且仅覆盖硅的一部分 盖层。

公开(公告)号：US20130119479A1

公开(公告)日：2013-05-16

申请号：US13736951

申请日：2013-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Han Hung ,  Tsai-Fu Chen ,  Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

IPC: H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the silicon cap layer, and covering only a portion of the silicon cap layer.

Abstract translation: 在本发明中提供一种晶体管结构。 晶体管结构包括：包括N型阱的衬底，设置在N型阱上的栅极，设置在栅极上的间隔物，位于衬垫下方的衬底中的第一轻掺杂区域，P型源极/漏极 位于栅极两侧的衬底中的覆盖P型源/漏区和第一轻掺杂区的硅帽层和设置在硅帽层上的硅化物层，并且仅覆盖硅的一部分 盖层。

公开(公告)号：US12176403B2

公开(公告)日：2024-12-24

申请号：US17737041

申请日：2022-05-05

Applicant: United Microelectronics Corp.

Inventor： Chi-Hsiao Chen ,  Tzyy-Ming Cheng ,  Wei Jen Chen ,  Kai Lin Lee

IPC: H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) device including the following components is provided. A gate electrode is located on a barrier layer. A source electrode is located on the first side of the gate electrode. A drain electrode is located on the second side of the gate. A source field plate is connected to the source electrode. The source field plate includes first, second, and third field plate portions. The first field plate portion is connected to the source electrode and is located on the first side of the gate electrode. The second field plate portion is located on the second side of the gate electrode. The third field plate portion is connected to the end of the first field plate portion and the end of the second field plate portion. The source field plate has a first opening located directly above the gate electrode.

公开(公告)号：US09954082B1

公开(公告)日：2018-04-24

申请号：US15598260

申请日：2017-05-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Ming Lee ,  Sheng-Hao Lin ,  Tzyy-Ming Cheng

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/66 ,  H01L27/11568 ,  H01L27/11521 ,  H01L29/51 ,  H01L21/027

CPC classification number: H01L29/66795 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: A method of fabricating an embedded nonvolatile memory device is disclosed. A semiconductor substrate having thereon a fin body protruding from an isolation layer is provided. A charge storage layer crossing the fin body is formed. An inter-layer dielectric layer is deposited on the semiconductor substrate. The inter-layer dielectric layer is polished to expose a top surface of the charge storage layer. The charge storage layer is then recess etched and cut into separate charge storage structures. A high-k dielectric layer is formed on the charge storage structures. A word line is formed on the high-k dielectric layer.

公开(公告)号：US20150380512A1

公开(公告)日：2015-12-31

申请号：US14848362

申请日：2015-09-09

Applicant: United Microelectronics Corp.

Inventor： Chan-Lon Yang ,  Chi-Mao Hsu ,  Chun-Yuan Wu ,  Tzyy-Ming Cheng ,  Shih-Fang Tzou ,  Chin-Fu Lin ,  Hsin-Fu Huang ,  Min-Chuan Tsai

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843

Abstract: A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ.

Abstract translation: 一种金属栅极结构的制造方法，其特征在于，具备在其上依次形成有高K栅极电介质层和底部阻挡层的基板，在基板上形成功函数金属层，对功函数金属层进行退火处理 原位。

公开(公告)号：US09281400B1

公开(公告)日：2016-03-08

申请号：US14726620

申请日：2015-06-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hsin-Yu Chen ,  Hao-Ming Lee ,  Tzyy-Ming Cheng

IPC: H01L21/339 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823493 ,  H01L21/8258

Abstract: A method of fabricating a semiconductor device with fin-shaped structures includes respectively forming first fin-shaped structures in a first region and a second region of a semiconductor substrate, depositing a dielectric layer to completely cover the first fin-shaped structures, removing the first fin-shaped structures in the second region so as to form trenches in the dielectric layer, and performing an in-situ doping epitaxial growth process so as to respectively form second fin-shaped structures in the trenches.

Abstract translation: 制造具有鳍状结构的半导体器件的方法包括分别在半导体衬底的第一区域和第二区域中形成第一鳍状结构，沉积介电层以完全覆盖第一鳍状结构，去除第一 在第二区域中形成鳍状结构，以便在电介质层中形成沟槽，并且进行原位掺杂外延生长工艺以在沟槽中分别形成第二鳍状结构。