公开(公告)号：US20250072221A1

公开(公告)日：2025-02-27

申请号：US18466855

申请日：2023-09-14

Applicant: United Microelectronics Corp.

Inventor： Shin-Hung Li

IPC: H10K59/122 ,  H01L21/311 ,  H10K59/173 ,  H10K71/60

Abstract: A manufacturing method of a semiconductor structure including the following steps is disclosed. A definition layer is formed on a substrate. The definition layer includes a first dielectric layer and a second dielectric layer. A first isotropic etching process is performed on the second dielectric layer to form a first opening in the second dielectric layer. A portion of the first opening is located under the patterned photoresist layer. A first anisotropic etching process is performed on the first dielectric layer to form a second opening in the first dielectric layer. The first opening is connected to the second opening to form a third opening. The patterned photoresist layer is removed. An etch back process is performed on the first dielectric layer and the second dielectric layer, so that a sidewall of the definition layer exposed by the third opening is an inclined surface.

公开(公告)号：US20250072035A1

公开(公告)日：2025-02-27

申请号：US18369209

申请日：2023-09-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li ,  Cheng-Yu Ho

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes a first oxide layer and a gate structure. The first oxide layer is disposed on a substrate. The gate structure is disposed on the first oxide layer. The gate structure includes a gate and a spacer surrounding the gate. The first oxide layer includes an exposed segment not covered by the gate structure. A thickness of the first oxide layer right below the gate is fixed, and the thickness of the first oxide layer right below the gate is greater than a thickness of the exposed segment.

公开(公告)号：US12080794B2

公开(公告)日：2024-09-03

申请号：US18139960

申请日：2023-04-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Nien-Chung Li ,  Chang-Po Hsiung

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7824 ,  H01L29/0649 ,  H01L29/1079 ,  H01L29/517 ,  H01L29/66689

Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

公开(公告)号：US10535734B2

公开(公告)日：2020-01-14

申请号：US16460813

申请日：2019-07-02

Applicant: United Microelectronics Corp.

Inventor： Shin-Hung Li ,  Kuan-Chuan Chen ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L21/8234 ,  H01L29/08 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L27/06

Abstract: Method for fabricating semiconductor device, including semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.

公开(公告)号：US20240347338A1

公开(公告)日：2024-10-17

申请号：US18755651

申请日：2024-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L21/02 ,  H01L21/8258 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/02565 ,  H01L21/8258 ,  H01L29/66969 ,  H01L29/7869

Abstract: The present invention provides a semiconductor structure, including a substrate, a thin-film transistor (TFT) on the substrate, wherein the thin-film transistor including a TFT channel layer, a first source and a first drain in the TFT channel layer and a first capping layer on the TFT channel layer. A MOSFET is on the substrate, with a second gate, a second source and a second drain on two sides of the second gate and a second capping layer on the second gate, wherein top surfaces of the second capping layer and the first capping layer are leveled, and a first ILD layer is on the first capping layer and the second capping layer, wherein the first ILD layer and the first capping layer function collectively as a gate dielectric layer for the TFT.

公开(公告)号：US20230253496A1

公开(公告)日：2023-08-10

申请号：US17688821

申请日：2022-03-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L29/0847 ,  H01L29/42392

Abstract: A semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor and a second transistor. The substrate includes a high-voltage region and a low-voltage region. The first transistor is disposed on the HV region, and includes a first gate dielectric layer disposed on a first base, and a first gate electrode on the first gate dielectric layer. The first gate dielectric layer includes a composite structure having a first dielectric layer and a second dielectric layer stacked sequentially. The second transistor is disposed on the LV region, and includes a fin shaped structure protruded from a second base on the substrate, and a second gate electrode disposed on the fin shaped structure. The first dielectric layer covers sidewalls of the second gate electrode and a top surface of the first dielectric layer is even with a top surface of the second gate electrode.

公开(公告)号：US20220223720A1

公开(公告)日：2022-07-14

申请号：US17160427

申请日：2021-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Ruei-Jhe Tsao ,  Ta-Wei Chiu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06

Abstract: A semiconductor structure includes a substrate having a first region and a second region around the first region. A first fin structure is disposed within the first region. A second fin structure is disposed within the second region. A first isolation trench is disposed within the first region and situated adjacent to the first fin structure. A first trench isolation layer is disposed in the first isolation trench. A second isolation trench is disposed around the first region and situated between the first fin structure and the second fin structure. The bottom surface of the second isolation trench has a step height. A second isolation layer is disposed in the second isolation trench.

公开(公告)号：US11251180B2

公开(公告)日：2022-02-15

申请号：US16430941

申请日：2019-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L29/76 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8234

Abstract: A transistor and a method for forming the same are provided. The transistor includes a semiconductor substrate, a gate dielectric layer, a gate electrode, a spacer, and a source/drain. The semiconductor substrate includes a protrusive semiconductor portion protruded from a lower surface of the semiconductor substrate. The gate dielectric layer is on the semiconductor substrate. The gate electrode is on the gate dielectric layer. The spacer is on a sidewall of the gate electrode. An outer surface of the spacer has a concave portion. The source/drain is in the semiconductor substrate.

公开(公告)号：US10923485B2

公开(公告)日：2021-02-16

申请号：US16842245

申请日：2020-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L27/112 ,  H01L23/525

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a resistive random access memory cell, and a semiconductor element. The resistive random access memory cell is on the substrate. The resistive random access memory cell includes a first electrode having a U shape. The semiconductor element is adjoined with an outer sidewall of the first electrode.

公开(公告)号：US10665597B2

公开(公告)日：2020-05-26

申请号：US15949368

申请日：2018-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L27/112 ,  H01L23/525

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a resistive random access memory cell, and a semiconductor element. The resistive random access memory cell is on the substrate. The resistive random access memory cell includes a first electrode having a U shape. The semiconductor element is adjoined with an outer sidewall of the first electrode.