公开(公告)号：US09659937B2

公开(公告)日：2017-05-23

申请号：US14683128

申请日：2015-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yun Chang ,  Chi-Mao Hsu ,  Wei-Ming Hsiao ,  Nien-Ting Ho ,  Kuo-Chih Lai

IPC: H01L27/092 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L27/0922 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor process of forming metal gates with different threshold voltages includes the following steps. A substrate having a first area and a second area is provided. A dielectric layer and a first work function layer are sequentially formed on the substrate of the first area and the second area. A second work function layer is directly formed on the first work function layer of the first area. A third work function layer is directly formed on the first work function layer of the second area, where the third work function layer is different from the second work function layer. The present invention also provides a semiconductor structure formed by said semiconductor process.

公开(公告)号：US09478628B1

公开(公告)日：2016-10-25

申请号：US14853956

申请日：2015-09-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Nien-Ting HO ,  Chi-Mao Hsu ,  Ching-Yun Chang ,  Yen-Chen Chen ,  Yang-Ju Lu ,  Shih-Min Chou ,  Yun-Tzu Chang ,  Hsiang-Chieh Yen ,  Min-Chuan Tsai

IPC: H01L21/4763 ,  H01L29/49 ,  H01L29/40 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L21/28088 ,  H01L29/66545

Abstract: A metal gate forming process includes the following steps. A first metal layer is formed on a substrate by at least a first step followed by a second step, wherein the processing power of the second step is higher than the processing power of the first step.

Abstract translation: 金属栅极形成工艺包括以下步骤。 第一金属层通过至少第一步骤和第二步骤形成在衬底上，其中第二步骤的处理能力高于第一步骤的处理能力。

公开(公告)号：US09728467B2

公开(公告)日：2017-08-08

申请号：US14880693

申请日：2015-10-12

Applicant: United Microelectronics Corp.

Inventor： Yun-Tzu Chang ,  Shih-Min Chou ,  Kuo-Chih Lai ,  Ching-Yun Chang ,  Hsiang-Chieh Yen ,  Yen-Chen Chen ,  Yang-Ju Lu ,  Nien-Ting Ho ,  Chi-Mao Hsu

IPC: H01L21/302 ,  H01L29/788 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L21/823842

Abstract: A method for modulating a work function of a semiconductor device having a metal gate structure including the following steps is provided. A first stacked gate structure and a second stacked gate structure having an identical structure are provided on a substrate. The first stacked gate structure and the second stacked gate structure respectively include a first work function metal layer of a first type. A patterned hard mask layer is formed. The patterned hard mask layer exposes the first work function metal layer of the first stacked gate structure and covers the first work function metal layer of the second stacked gate structure. A first gas treatment is performed to the first work function metal layer of the first stacked gate structure exposed by the patterned hard mask layer. A gas used in the first gas treatment includes nitrogen-containing gas or oxygen-containing gas.

公开(公告)号：US20170148891A1

公开(公告)日：2017-05-25

申请号：US14951446

申请日：2015-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Yun-Tzu Chang ,  Wei-Ming Hsiao ,  Nien-Ting Ho ,  Shih-Min Chou ,  Yang-Ju Lu ,  Ching-Yun Chang ,  Yen-Chen Chen ,  Kuan-Chun Lin ,  Chi-Mao Hsu

IPC: H01L29/51 ,  H01L29/49 ,  H01L29/40

CPC classification number: H01L29/513 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/517

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

公开(公告)号：US20170076995A1

公开(公告)日：2017-03-16

申请号：US14880693

申请日：2015-10-12

Applicant: United Microelectronics Corp.

Inventor： Yun-Tzu Chang ,  Shih-Min Chou ,  Kuo-Chih Lai ,  Ching-Yun Chang ,  Hsiang-Chieh Yen ,  Yen-Chen Chen ,  Yang-Ju Lu ,  Nien-Ting Ho ,  Chi-Mao Hsu

IPC: H01L21/8238

CPC classification number: H01L21/823842

Abstract: A method for modulating a work function of a semiconductor device having a metal gate structure including the following steps is provided. A first stacked gate structure and a second stacked gate structure having an identical structure are provided on a substrate. The first stacked gate structure and the second stacked gate structure respectively include a first work function metal layer of a first type. A patterned hard mask layer is formed. The patterned hard mask layer exposes the first work function metal layer of the first stacked gate structure and covers the first work function metal layer of the second stacked gate structure. A first gas treatment is performed to the first work function metal layer of the first stacked gate structure exposed by the patterned hard mask layer. A gas used in the first gas treatment includes nitrogen-containing gas or oxygen-containing gas.

Abstract translation: 提供了一种用于调制具有包括以下步骤的金属栅极结构的半导体器件的功函数的方法。 在基板上设置具有相同结构的第一堆叠栅极结构和第二堆叠栅极结构。 第一堆叠栅极结构和第二堆叠栅极结构分别包括第一类型的第一功函数金属层。 形成图案化的硬掩模层。 图案化的硬掩模层暴露第一堆叠栅极结构的第一功函数金属层并且覆盖第二堆叠栅极结构的第一功函数金属层。 对由图案化的硬掩模层暴露的第一堆叠栅极结构的第一功函数金属层进行第一气体处理。 在第一气体处理中使用的气体包括含氮气体或含氧气体。

公开(公告)号：US20160268259A1

公开(公告)日：2016-09-15

申请号：US14683128

申请日：2015-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yun Chang ,  Chi-Mao Hsu ,  Wei-Ming Hsiao ,  Nien-Ting Ho ,  Kuo-Chih Lai

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/285 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L27/0922 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor process of forming metal gates with different threshold voltages includes the following steps. A substrate having a first area and a second area is provided. A dielectric layer and a first work function layer are sequentially formed on the substrate of the first area and the second area. A second work function layer is directly formed on the first work function layer of the first area. A third work function layer is directly formed on the first work function layer of the second area, where the third work function layer is different from the second work function layer. The present invention also provides a semiconductor structure formed by said semiconductor process.

Abstract translation: 形成具有不同阈值电压的金属栅极的半导体工艺包括以下步骤。 提供具有第一区域和第二区域的衬底。 介电层和第一功函数层依次形成在第一区域和第二区域的基板上。 第二功能层直接形成在第一区域的第一功能层上。 第三功函数层直接形成在第二区域的第一功函数层上，其中第三功函数层与第二功函数层不同。 本发明还提供了由所述半导体工艺形成的半导体结构。

公开(公告)号：US11139384B2

公开(公告)日：2021-10-05

申请号：US16561002

申请日：2019-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Yun-Tzu Chang ,  Wei-Ming Hsiao ,  Nien-Ting Ho ,  Shih-Min Chou ,  Yang-Ju Lu ,  Ching-Yun Chang ,  Yen-Chen Chen ,  Kuan-Chun Lin ,  Chi-Mao Hsu

IPC: H01L29/43 ,  H01L29/51 ,  H01L29/40 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

公开(公告)号：US20200006514A1

公开(公告)日：2020-01-02

申请号：US16561002

申请日：2019-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Yun-Tzu Chang ,  Wei-Ming Hsiao ,  Nien-Ting Ho ,  Shih-Min Chou ,  Yang-Ju Lu ,  Ching-Yun Chang ,  Yen-Chen Chen ,  Kuan-Chun Lin ,  Chi-Mao Hsu

IPC: H01L29/51 ,  H01L29/40 ,  H01L29/49

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

公开(公告)号：US09691704B1

公开(公告)日：2017-06-27

申请号：US15175299

申请日：2016-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Chia-Chang Hsu ,  Nien-Ting Ho ,  Ching-Yun Chang ,  Yen-Chen Chen ,  Shih-Min Chou ,  Yun-Tzu Chang ,  Yang-Ju Lu ,  Wei-Ming Hsiao ,  Wei-Ning Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/76 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L23/528 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor structure comprises a first wire level, a second wire level and a via level. The first wire level comprises a first conductive feature. The second wire level is disposed on the first wire level. The second wire level comprises a second conductive feature and a third conductive feature. The via level is disposed between the first wire level and the second wire level. The via level comprises a via connecting the first conductive feature and the second conductive feature. There is a first air gap between the first conductive feature and the second conductive feature. There is a second air gap between the second conductive feature and the third conductive feature. The first air gap and the second air gap are linked.

公开(公告)号：US20150061042A1

公开(公告)日：2015-03-05

申请号：US14016234

申请日：2013-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsun-Min Cheng ,  Nien-Ting Ho ,  Chien-Hao Chen ,  Ching-Yun Chang ,  Hsin-Fu Huang ,  Min-Chuan Tsai ,  Chi-Yuan Sun ,  Chi-Mao Hsu

IPC: H01L29/49 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/285

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A metal gate structure is provided. The metal gate structure includes a semiconductor substrate, a gate dielectric layer, a multi-layered P-type work function layer and a conductive metal layer. The gate dielectric layer is disposed on the semiconductor substrate. The multi-layered P-type work function layer is disposed on the gate dielectric layer, and the multi-layered P-type work function layer includes at least a crystalline P-type work function layer and at least an amorphous P-type work function layer. Furthermore, the conductive metal layer is disposed on the multi-layered P-type work function layer.

Abstract translation: 提供了金属栅极结构。 金属栅极结构包括半导体衬底，栅极电介质层，多层P型功函数层和导电金属层。 栅极电介质层设置在半导体衬底上。 多层P型功函数层设置在栅极电介质层上，多层P型功函数层至少包含结晶P型功函数层和至少一非晶P型功函数层 层。 此外，导电性金属层设置在多层P型功函数层上。