公开(公告)号：US11107689B2

公开(公告)日：2021-08-31

申请号：US16207201

申请日：2018-12-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ming-Shiou Hsieh ,  Rong-Sin Lin ,  Ching-I Li ,  Neng-Hui Yang

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a pad oxide layer on the substrate, wherein the pad oxide layer comprises a first thickness; performing an implantation process to inject germanium (Ge) into the substrate on the PMOS region; performing a first cleaning process to reduce the first thickness of the pad oxide layer on the PMOS region to a second thickness; performing an anneal process; and performing a second cleaning process to remove the pad oxide layer.

公开(公告)号：US09947588B1

公开(公告)日：2018-04-17

申请号：US15817274

申请日：2017-11-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Neng-Hui Yang ,  Tsai-Yu Wen ,  Ching-I Li

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/823431 ,  H01L21/02115 ,  H01L21/02271 ,  H01L21/265 ,  H01L21/324 ,  H01L21/823468 ,  H01L21/823481

Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.

公开(公告)号：US11664425B2

公开(公告)日：2023-05-30

申请号：US17580622

申请日：2022-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234

CPC classification number: H01L29/105 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26533 ,  H01L21/324 ,  H01L21/823412 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

公开(公告)号：US10651275B2

公开(公告)日：2020-05-12

申请号：US15893681

申请日：2018-02-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

公开(公告)号：US20190214465A1

公开(公告)日：2019-07-11

申请号：US15893681

申请日：2018-02-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

公开(公告)号：US09859164B1

公开(公告)日：2018-01-02

申请号：US15294792

申请日：2016-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Neng-Hui Yang ,  Tsai-Yu Wen ,  Ching-I Li

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/324 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/02115 ,  H01L21/02271 ,  H01L21/265 ,  H01L21/324 ,  H01L21/823468 ,  H01L21/823481

Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.

公开(公告)号：US20150104914A1

公开(公告)日：2015-04-16

申请号：US14551922

申请日：2014-11-24

Applicant: United Microelectronics Corp.

Inventor： Chan-Lon Yang ,  Ching-Nan Hwang ,  Chi-Heng Lin ,  Chun-Yao Yang ,  Ger-Pin Lin ,  Ching-I Li

IPC: H01L21/265 ,  H01L21/02 ,  H01L21/3215 ,  H01L49/02 ,  H01L27/06

CPC classification number: H01L21/26593 ,  H01L21/02532 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/76224 ,  H01L27/0629 ,  H01L28/20

Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. The polysilicon layer is cryo-implanted with at least two of multiple species including a germanium species, a carbon species and a p- or n-type species, at a temperature ranging between −40° C. and −120° C. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating.

Abstract translation: 提供半导体工艺，包括以下步骤。 在基板上形成多晶硅层。 多晶硅层在-40℃至-120℃的温度范围内用至少两种多种物质进行低温注入，包括锗物质，碳物质和p型或n型物质。不对称 对多晶硅层进行双面加热处理，其中用于正面加热的功率与用于背面加热的功率不同。

公开(公告)号：US20180108570A1

公开(公告)日：2018-04-19

申请号：US15817274

申请日：2017-11-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Neng-Hui Yang ,  Tsai-Yu Wen ,  Ching-I Li

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324

CPC classification number: H01L21/823431 ,  H01L21/02115 ,  H01L21/02271 ,  H01L21/265 ,  H01L21/324 ,  H01L21/823468 ,  H01L21/823481

Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.

公开(公告)号：US20130122691A1

公开(公告)日：2013-05-16

申请号：US13707613

申请日：2012-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-I Liao ,  Ching-I Li ,  Shu-Yen Chan

IPC: H01L21/20

CPC classification number: H01L21/20 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A method for forming a semiconductor structure is provided. First, multiple recesses are formed in a substrate. Second, a precursor mixture is provided to form a non-doped epitaxial layer on the inner surface of the recesses. The precursor mixture includes a silicon precursor, an epitaxial material precursor and a hydrogen-halogen compound. The flow rate ratio of the silicon precursor to the epitaxial material precursor is greater than 1.7. Later, a doped epitaxial layer including Si, the epitaxial material and the dopant is formed and substantially fills up the recess.

Abstract translation: 提供一种形成半导体结构的方法。 首先，在基板上形成多个凹部。 第二，提供前体混合物以在凹槽的内表面上形成非掺杂外延层。 前体混合物包括硅前体，外延材料前体和氢卤素化合物。 硅前体与外延材料前体的流速比大于1.7。 之后，形成包括Si，外延材料和掺杂剂的掺杂外延层，并基本上填充凹槽。

公开(公告)号：US11271078B2

公开(公告)日：2022-03-08

申请号：US16836953

申请日：2020-04-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234

Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.