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公开(公告)号：US20200321273A1
公开(公告)日：2020-10-08
申请号：US16886728
申请日：2020-05-28
Applicant: UTAC Headquarters Pte. Ltd.
Inventor： Hua Hong TAN , Wilson Poh Leng ONG , Kriangsak Sae LE , Saravuth SIRINORAKUL , Somsak PHUKRONGHIN , Paweena PHATTO
IPC: H01L23/498 , H01L23/16 , H01L23/31 , H01L21/48 , H01L21/52 , H01L21/56 , H01L23/055 , H01L23/04 , H01L23/24
Abstract: A method for forming a semiconductor package is disclosed herein. The method includes forming a package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate includes a recess region below the first major surface defined with a die region and a non-die region surrounding the die region. A semiconductor die is disposed in the die region within the recess region. A dam structure is disposed within the recess region. The dam structure surrounds the semiconductor die and extends upwardly to a height below the first major surface of the package substrate. The method also includes dispensing a liquid encapsulant material into the recess region. The liquid encapsulant material is surrounded by the dam structure and extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate.
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公开(公告)号：US20170077007A1
公开(公告)日：2017-03-16
申请号：US15361487
申请日：2016-11-27
Applicant: UTAC Headquarters Pte. Ltd.
Inventor： Nathapong SUTHIWONGSUNTHORN , Antonio Jr. Bambalan DIMAANO , Rui HUANG , Hua Hong TAN , Kriangsak Sae LE , Beng Yeung HO , Nelson Agbisit DE VERA , Roel Adeva ROBLES , Wedanni Linsangan MICLA
IPC: H01L23/31 , H01L23/544 , H01L21/683 , H01L21/56 , H01L21/78
CPC classification number: H01L23/3135 , H01L21/3105 , H01L21/561 , H01L21/566 , H01L21/568 , H01L21/6836 , H01L21/78 , H01L23/3114 , H01L23/544 , H01L24/11 , H01L24/13 , H01L24/94 , H01L2221/68327 , H01L2221/68336 , H01L2221/6834 , H01L2223/54426 , H01L2224/0391 , H01L2224/1134 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/94 , H01L2924/10156 , H01L2924/1815 , H01L2224/11 , H01L2924/014 , H01L2924/00014
Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.
Abstract translation: 公开了用于形成半导体封装的半导体封装和方法。 该方法包括提供具有第一和第二主表面的晶片。 晶片由多个管芯和设置在晶片的第一主表面上的多个外部电触点制成。 该方法包括处理晶片。 处理晶片包括将晶片分离成多个单独的芯片。 单个管芯包括第一和第二主表面以及第一和第二侧壁，并且外部电触头形成在管芯的第一主表面上。 形成密封剂材料。 密封剂材料覆盖模具的第一和第二侧壁的至少一部分。
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公开(公告)号：US20150357256A1
公开(公告)日：2015-12-10
申请号：US14731484
申请日：2015-06-05
Applicant: UTAC Headquarters Pte. Ltd.
Inventor： Nathapong SUTHIWONGSUNTHORN , Antonio Jr. Bambalan DIMAANO , Rui HUANG , Hua Hong TAN , Kriangsak Sae LE , Beng Yeung HO , Nelson Agbisit DE VERA , Roel Adeva ROBLES , Wedanni Linsangan MICLA
IPC: H01L23/31 , H01L21/3105 , H01L21/78 , H01L21/683 , H01L23/00 , H01L21/56
CPC classification number: H01L23/3135 , H01L21/3105 , H01L21/561 , H01L21/566 , H01L21/568 , H01L21/6836 , H01L21/78 , H01L23/3114 , H01L23/544 , H01L24/11 , H01L24/13 , H01L24/94 , H01L2221/68327 , H01L2221/68336 , H01L2221/6834 , H01L2223/54426 , H01L2224/0391 , H01L2224/1134 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/94 , H01L2924/10156 , H01L2924/1815 , H01L2224/11 , H01L2924/014 , H01L2924/00014
Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.
Abstract translation: 公开了用于形成半导体封装的半导体封装和方法。 该方法包括提供具有第一和第二主表面的晶片。 晶片由多个管芯和设置在晶片的第一主表面上的多个外部电触点制成。 该方法包括处理晶片。 处理晶片包括将晶片分离成多个单独的芯片。 单个管芯包括第一和第二主表面以及第一和第二侧壁，并且外部电触头形成在管芯的第一主表面上。 形成密封剂材料。 密封剂材料覆盖模具的第一和第二侧壁的至少一部分。
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公开(公告)号：US20190043797A1
公开(公告)日：2019-02-07
申请号：US16056541
申请日：2018-08-07
Applicant: UTAC Headquarters Pte. Ltd.
Inventor： Hua Hong TAN , Wilson Poh Leng ONG , Kriangsak Sae LE , Saravuth SIRINORAKUL , Somsak PHUKRONGHIN , Paweena PHATTO
IPC: H01L23/498 , H01L23/00 , H01L23/16 , H01L23/31 , H01L23/055 , H01L21/48 , H01L21/52 , H01L21/56
Abstract: An improved method for forming a semiconductor package is disclosed herein. The method includes forming a multi-layer package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate comprises a recess region. A semiconductor die is attached to the die region within the recess region. A dam structure is formed within the recess region. The dam structure surrounds the semiconductor die and extends upward to a height below the first major surface of the package substrate. A liquid encapsulant material is dispensed into the recess region. The liquid encapsulant material is surrounded by the dam structure. The liquid encapsulant extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate.
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公开(公告)号：US20180240726A1
公开(公告)日：2018-08-23
申请号：US15961839
申请日：2018-04-24
Applicant: UTAC Headquarters Pte. Ltd.
Inventor： Nathapong SUTHIWONGSUNTHORN , Antonio Jr. Bambalan DIMAANO , Rui HUANG , Hua Hong TAN , Kriangsak Sae LE , Beng Yeung HO , Nelson Agbisit DE VERA , Roel Adeva ROBLES , Wedanni Linsangan MICLA
IPC: H01L23/31 , H01L23/544 , H01L21/56 , H01L21/683 , H01L21/78 , H01L21/3105 , H01L23/00
CPC classification number: H01L23/3135 , H01L21/3105 , H01L21/561 , H01L21/566 , H01L21/568 , H01L21/6836 , H01L21/78 , H01L23/3114 , H01L23/544 , H01L24/11 , H01L24/13 , H01L24/94 , H01L2221/68327 , H01L2221/68336 , H01L2221/6834 , H01L2223/54426 , H01L2224/0391 , H01L2224/1134 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/94 , H01L2924/10156 , H01L2924/1815 , H01L2224/11 , H01L2924/014 , H01L2924/00014
Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.
