公开(公告)号：US20140256115A1

公开(公告)日：2014-09-11

申请号：US14285645

申请日：2014-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chien Liu ,  Chia-Lung Chang ,  Jei-Ming Chen ,  Jui-Min Lee ,  Yuh-Min Lin

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L29/0649

Abstract: A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.

Abstract translation: 半导体结构位于衬底的凹部中。 半导体结构包括衬垫，富硅层和填充材料。 衬垫位于凹槽的表面上。 富硅层位于衬套上。 填充材料位于富硅层上并填充凹槽。 此外，还提供了形成所述半导体结构的半导体工艺。

公开(公告)号：US09034726B2

公开(公告)日：2015-05-19

申请号：US14285645

申请日：2014-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chien Liu ,  Chia-Lung Chang ,  Jei-Ming Chen ,  Jui-Min Lee ,  Yuh-Min Lin

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L29/0649

Abstract: A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.

Abstract translation: 半导体结构位于衬底的凹部中。 半导体结构包括衬垫，富硅层和填充材料。 衬垫位于凹槽的表面上。 富硅层位于衬套上。 填充材料位于富硅层上并填充凹槽。 此外，还提供了形成所述半导体结构的半导体工艺。

公开(公告)号：US20160020139A1

公开(公告)日：2016-01-21

申请号：US14478609

申请日：2014-09-05

Applicant: United Microelectronics Corp.

Inventor： Wen-Yi Teng ,  Yuh-Min Lin ,  Chih-Chien Liu ,  Chieh-Wen Lo

IPC: H01L21/762 ,  H01L23/58 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02219 ,  H01L21/02271 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67742 ,  H01L21/67766 ,  H01L21/762 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A gap-filling dielectric layer, method for fabricating the same and applications thereof are disclosed. A silicon-containing dielectric layer is firstly deposited on a substrate. The silicon-containing dielectric layer is then subjected to a curing process, an in-situ wetting treatment and an annealing process in sequence, whereby a gap-filling dielectric layer with a nitrogen atom density less than 1×1022 atoms/cm3 is formed.

Abstract translation: 公开了间隙填充介电层，其制造方法及其应用。 首先在基板上沉积含硅介电层。 然后对含硅电介质层进行固化处理，原位润湿处理和退火处理，由此形成氮原子密度小于1×1022原子/ cm3的间隙填充介电层。

公开(公告)号：US09034759B2

公开(公告)日：2015-05-19

申请号：US13740249

申请日：2013-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jei-Ming Chen ,  Yuh-Min Lin

IPC: H01L21/768

CPC classification number: H01L21/76819 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A method for forming an interlevel dielectric (ILD) layer includes the following steps. A MOS transistor on a substrate is provided. A first undoped oxide layer is deposited to cover the substrate and the MOS transistor. The first undoped oxide layer is planarized. A phosphorus containing oxide layer is deposited on the first undoped oxide layer. A second undoped oxide layer is deposited on the phosphorus containing oxide layer.

Abstract translation: 形成层间电介质（ILD）层的方法包括以下步骤。 提供了衬底上的MOS晶体管。 沉积第一未掺杂的氧化物层以覆盖衬底和MOS晶体管。 第一未掺杂的氧化物层被平坦化。 含磷氧化物层沉积在第一未掺杂氧化物层上。 在含磷氧化物层上沉积第二未掺杂的氧化物层。

公开(公告)号：US20140199836A1

公开(公告)日：2014-07-17

申请号：US13740249

申请日：2013-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jei-Ming Chen ,  Yuh-Min Lin

IPC: H01L21/768

CPC classification number: H01L21/76819 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A method for forming an interlevel dielectric (ILD) layer includes the following steps. A MOS transistor on a substrate is provided. A first undoped oxide layer is deposited to cover the substrate and the MOS transistor. The first undoped oxide layer is planarized. A phosphorus containing oxide layer is deposited on the first undoped oxide layer. A second undoped oxide layer is deposited on the phosphorus containing oxide layer.

Abstract translation: 形成层间电介质（ILD）层的方法包括以下步骤。 提供了衬底上的MOS晶体管。 沉积第一未掺杂的氧化物层以覆盖衬底和MOS晶体管。 第一未掺杂的氧化物层被平坦化。 含磷氧化物层沉积在第一未掺杂氧化物层上。 在含磷氧化物层上沉积第二未掺杂的氧化物层。

公开(公告)号：US08742587B1

公开(公告)日：2014-06-03

申请号：US13680102

申请日：2012-11-18

Applicant: United Microelectronics Corp.

Inventor： Yuh-Min Lin ,  Wen-Ting Chen ,  Yi-Yu Wu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/52 ,  H01L21/768 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76826 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal interconnection structure includes a substrate and a protective layer. The substrate includes at least a first conductive layer. The protective layer is a single-layered structure disposed on the substrate, and a quantity of oxygen (O) in an upper part of the protective layer is more than a quantity of oxygen (O) in a lower part of the protective layer. A material of the upper part of the protective layer includes silicon oxycarbide (SiCO) or silicon oxycarbonitride (SiCNO), and a material of the lower part of the protective layer includes silicon carbide (SiC) or silicon carbonitride (SiCN).

Abstract translation: 金属互连结构包括基板和保护层。 衬底至少包括第一导电层。 保护层是设置在基板上的单层结构，保护层的上部的氧（O）的量比保护层的下部的氧（O）的量多。 保护层上部的材料包括碳氧化硅（SiCO）或硅碳氮氧化物（SiCNO），保护层下部的材料包括碳化硅（SiC）或碳氮化硅（SiCN）。

公开(公告)号：US20140138830A1

公开(公告)日：2014-05-22

申请号：US13680102

申请日：2012-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuh-Min Lin ,  Wen-Ting Chen ,  Yi-Yu Wu

IPC: H01L23/52 ,  H01L21/768

CPC classification number: H01L23/52 ,  H01L21/768 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76826 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal interconnection structure includes a substrate and a protective laver. The substrate includes at least a first conductive layer. The protective layer is a single-layered structure disposed on the substrate, and a quantity of oxygen (O) in an upper part of the protective layer is more than a quantity of oxygen (O) in a lower part of the protective layer. A material of the upper part of the protective layer includes silicon oxycarbide (SiCO) or silicon oxycarbonitride (SiCNO), and a material of the lower part of the protective layer includes silicon carbide (SiC) or silicon carbonitride (SiCN).

Abstract translation: 金属互连结构包括基底和保护性紫菜。 衬底至少包括第一导电层。 保护层是设置在基板上的单层结构，保护层的上部的氧（O）的量比保护层的下部的氧（O）的量多。 保护层上部的材料包括碳氧化硅（SiCO）或硅碳氮氧化物（SiCNO），保护层下部的材料包括碳化硅（SiC）或碳氮化硅（SiCN）。