公开(公告)号：US20130119479A1

公开(公告)日：2013-05-16

申请号：US13736951

申请日：2013-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Han Hung ,  Tsai-Fu Chen ,  Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

IPC: H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the silicon cap layer, and covering only a portion of the silicon cap layer.

Abstract translation: 在本发明中提供一种晶体管结构。 晶体管结构包括：包括N型阱的衬底，设置在N型阱上的栅极，设置在栅极上的间隔物，位于衬垫下方的衬底中的第一轻掺杂区域，P型源极/漏极 位于栅极两侧的衬底中的覆盖P型源/漏区和第一轻掺杂区的硅帽层和设置在硅帽层上的硅化物层，并且仅覆盖硅的一部分 盖层。

公开(公告)号：US08823109B2

公开(公告)日：2014-09-02

申请号：US13736951

申请日：2013-01-09

Applicant: United Microelectronics Corp.

Inventor： Wen-Han Hung ,  Tsai-Fu Chen ,  Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the silicon cap layer, and covering only a portion of the silicon cap layer.

Abstract translation: 在本发明中提供一种晶体管结构。 晶体管结构包括：包括N型阱的衬底，设置在N型阱上的栅极，设置在栅极上的间隔物，位于衬垫下方的衬底中的第一轻掺杂区域，P型源极/漏极 位于栅极两侧的衬底中的覆盖P型源/漏区和第一轻掺杂区的硅帽层和设置在硅帽层上的硅化物层，并且仅覆盖硅的一部分 盖层。

公开(公告)号：US20140339652A1

公开(公告)日：2014-11-20

申请号：US14449157

申请日：2014-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Guang-Yaw Hwang ,  Chun-Hsien Lin ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Yi-Wen Chen ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Tong-Jyun Huang ,  Jie-Ning Yang ,  Tsung-Lung Tsai ,  Po-Jui Liao ,  Chien-Ming Lai ,  Ying-Tsung Chen ,  Cheng-Yu Ma ,  Wen-Han Hung ,  Che-Hua Hsu

IPC: H01L29/51 ,  H01L29/49

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846

Abstract: A semiconductor device with oxygen-containing metal gates includes a substrate, a gate dielectric layer and a multi-layered stack structure. The multi-layered stack structure is disposed on the substrate. At least one layer of the multi-layered stack structure includes a work function metal layer. The concentration of oxygen in the side of one layer of the multi-layered stack structure closer to the gate dielectric layer is less than that in the side of one layer of the multi-layered stack structure opposite to the gate dielectric layer.

Abstract translation: 具有含氧金属栅极的半导体器件包括衬底，栅介质层和多层堆叠结构。 多层堆叠结构设置在基板上。 多层堆叠结构的至少一层包括功函数金属层。 更靠近栅介质层的多层堆叠结构的一层侧的氧的浓度小于与栅介质层相反的多层堆叠结构的一层的一侧的浓度。