公开(公告)号：US20240395883A1

公开(公告)日：2024-11-28

申请号：US18210638

申请日：2023-06-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ta-Wei Chiu ,  Ping-Hung Chiang ,  Chia-Ling Wang ,  Wei-Lun Huang ,  Chia-Wen Lu ,  Yueh-Chang Lin

IPC: H01L29/423 ,  H01L21/308 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor structure with flush shallow trench isolation and gate oxide, including performing a first etching process to remove a pad oxide layer at one side of a STI and recess the substrate, the first etching process also forms a recess portion not covered by the first etching process and a protruding portion covered by the first etching process on the STI, forming a gate oxide layer on the recessed substrate, performing a second etching process to remove the protruding portion and the pad oxide layer and a first oxide layer on a drain region, performing a third etching process to remove a part of the STI and a second oxide layer, so that a top plane of the STI is flush with the gate oxide layer.

公开(公告)号：US20240355873A1

公开(公告)日：2024-10-24

申请号：US18762679

申请日：2024-07-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ling Wang ,  Ping-Hung Chiang ,  Wei-Lun Huang ,  Chia-Wen Lu ,  Ta-Wei Chiu

IPC: H01L29/06 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/823481

Abstract: A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A trench isolation structure is disposed in the substrate between the first device region and the second device region. The trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is coplanar with the second bottom surface.

公开(公告)号：US20230223306A1

公开(公告)日：2023-07-13

申请号：US17672638

申请日：2022-02-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ta-Wei Chiu ,  Ping-Hung Chiang ,  Chia-Wen Lu ,  Chia-Ling Wang ,  Wei-Lun Huang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/762

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L27/088

Abstract: Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.

公开(公告)号：US10811272B2

公开(公告)日：2020-10-20

申请号：US16261578

申请日：2019-01-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsin Liu ,  Ta-Wei Chiu ,  Chia-Lung Chang ,  Po-Chun Chen ,  Hong-Yi Fang ,  Yi-Wei Chen

IPC: H01L21/3105 ,  H01L21/027 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/108 ,  H01L29/66

Abstract: A method of forming a dielectric layer includes the following steps. A substrate including a first area and a second area is provided. A plurality of patterns on the substrate of the first area and a blanket stacked structure on the substrate of the second area are formed. An organic dielectric layer covers the patterns, the blanket stacked structure and the substrate. The blanket stacked structure is patterned by serving the organic dielectric layer as a hard mask layer, thereby forming a plurality of stacked structures. The organic dielectric layer is removed. A dielectric layer blanketly covers the patterns, the stacked structures, and the substrate.

公开(公告)号：US20200227269A1

公开(公告)日：2020-07-16

申请号：US16261578

申请日：2019-01-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsin Liu ,  Ta-Wei Chiu ,  Chia-Lung Chang ,  Po-Chun Chen ,  Hong-Yi Fang ,  Yi-Wei Chen

IPC: H01L21/3105 ,  H01L27/108 ,  H01L21/027 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02

Abstract: A method of forming a dielectric layer includes the following steps. A substrate including a first area and a second area is provided. A plurality of patterns on the substrate of the first area and a blanket stacked structure on the substrate of the second area are formed. An organic dielectric layer covers the patterns, the blanket stacked structure and the substrate. The blanket stacked structure is patterned by serving the organic dielectric layer as a hard mask layer, thereby forming a plurality of stacked structures. The organic dielectric layer is removed. A dielectric layer blanketly covers the patterns, the stacked structures, and the substrate.

公开(公告)号：US12183809B2

公开(公告)日：2024-12-31

申请号：US17673819

申请日：2022-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Huang ,  Chia-Ling Wang ,  Chia-Wen Lu ,  Ta-Wei Chiu ,  Ping-Hung Chiang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/423

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first recess and a second recess are formed in a first region and a second region of a semiconductor substrate, respectively. A bottom surface of the first recess is lower than a bottom surface of the second recess in a vertical direction. A first gate oxide layer and a second gate oxide layer are formed concurrently. At least a portion of the first gate oxide layer is formed in the first recess, and at least a portion of the second gate oxide layer is formed in the second recess. A removing process is performed for removing a part of the second gate oxide layer. A thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer after the removing process.

公开(公告)号：US20230231035A1

公开(公告)日：2023-07-20

申请号：US17673819

申请日：2022-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Huang ,  Chia-Ling Wang ,  Chia-Wen Lu ,  Ta-Wei Chiu ,  Ping-Hung Chiang

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/8234

CPC classification number: H01L29/66704 ,  H01L29/401 ,  H01L21/823462 ,  H01L29/42364

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first recess and a second recess are formed in a first region and a second region of a semiconductor substrate, respectively. A bottom surface of the first recess is lower than a bottom surface of the second recess in a vertical direction. A first gate oxide layer and a second gate oxide layer are formed concurrently. At least a portion of the first gate oxide layer is formed in the first recess, and at least a portion of the second gate oxide layer is formed in the second recess. A removing process is performed for removing a part of the second gate oxide layer. A thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer after the removing process.

公开(公告)号：US20230207620A1

公开(公告)日：2023-06-29

申请号：US17577403

申请日：2022-01-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ling Wang ,  Ping-Hung Chiang ,  Wei-Lun Huang ,  Chia-Wen Lu ,  Ta-Wei Chiu

IPC: H01L29/06 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/823481

Abstract: A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A trench isolation structure is disposed in the substrate between the first device region and the second device region. The trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is coplanar with the second bottom surface.

公开(公告)号：US11515404B2

公开(公告)日：2022-11-29

申请号：US17160427

申请日：2021-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Ruei-Jhe Tsao ,  Ta-Wei Chiu

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/11 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/08 ,  H01L27/092 ,  H01L27/02

Abstract: A semiconductor structure includes a substrate having a first region and a second region around the first region. A first fin structure is disposed within the first region. A second fin structure is disposed within the second region. A first isolation trench is disposed within the first region and situated adjacent to the first fin structure. A first trench isolation layer is disposed in the first isolation trench. A second isolation trench is disposed around the first region and situated between the first fin structure and the second fin structure. The bottom surface of the second isolation trench has a step height. A second isolation layer is disposed in the second isolation trench.

公开(公告)号：US12100624B2

公开(公告)日：2024-09-24

申请号：US17672638

申请日：2022-02-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ta-Wei Chiu ,  Ping-Hung Chiang ,  Chia-Wen Lu ,  Chia-Ling Wang ,  Wei-Lun Huang

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L27/088

Abstract: Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.