公开(公告)号：US20230207668A1

公开(公告)日：2023-06-29

申请号：US18118115

申请日：2023-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Fu Chang ,  Kuan-Hung Chen ,  Guang-Yu Lo ,  Chun-Chia Chen ,  Chun-Tsen Lu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/66795 ,  H01L29/785 ,  H01L29/7834 ,  H01L29/511 ,  H01L21/022 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/28202

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

公开(公告)号：US10043718B1

公开(公告)日：2018-08-07

申请号：US15672325

申请日：2017-08-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Hung Chen ,  Rung-Yuan Lee ,  Chun-Tsen Lu ,  Chorng-Lih Young

IPC: H01L21/02 ,  H01L21/8238 ,  H01L21/20 ,  H01L21/225 ,  H01L29/16 ,  H01L21/8234 ,  H01L21/04 ,  H01L21/762 ,  H01L29/66 ,  H01L29/165 ,  H01L21/22 ,  H01L29/78

Abstract: A method of fabricating a semiconductor device includes the following steps: providing a semiconductor substrate having a fin structure thereon; forming a recess in the fin structure so that the semiconductor substrate is partially exposed from the bottom surface of the recess; forming a dopant source layer conformally disposed on side surfaces and a bottom surface of the recess; removing the dopant source layer disposed on the bottom surface of the recess until portions of the semiconductor substrate are exposed from the bottom surface of the recess; and annealing the dopant source layer so as to form a side doped region in the fin structure.

公开(公告)号：US20240282843A1

公开(公告)日：2024-08-22

申请号：US18653933

申请日：2024-05-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Fu Chang ,  Kuan-Hung Chen ,  Guang-Yu Lo ,  Chun-Chia Chen ,  Chun-Tsen Lu

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/28202 ,  H01L29/511 ,  H01L29/7834 ,  H01L29/785

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

公开(公告)号：US10475744B2

公开(公告)日：2019-11-12

申请号：US15727380

申请日：2017-10-06

Applicant: United Microelectronics Corp.

Inventor： Kuan-Hung Chen ,  Rung-Yuan Lee ,  Chun-Tsen Lu

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/762 ,  H01L29/423 ,  H01L29/06 ,  B82Y99/00

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, an isolation structure, an outer structure, and a gate structure. The isolation structure is disposed on the substrate. The outer structure surrounds a sidewall of the isolation structure. The gate structure surrounds a central part of the outer structure, so that the central part covered by the gate structure becomes a channel region, and the outer structure at both sides of the central part respectively becomes a source region and a drain region.

公开(公告)号：US20190074250A1

公开(公告)日：2019-03-07

申请号：US15727380

申请日：2017-10-06

Applicant: United Microelectronics Corp.

Inventor： Kuan-Hung Chen ,  Rung-Yuan Lee ,  Chun-Tsen Lu

IPC: H01L23/532 ,  H01L21/762 ,  H01L21/02

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, an isolation structure, an outer structure, and a gate structure. The isolation structure is disposed on the substrate. The outer structure surrounds a sidewall of the isolation structure. The gate structure surrounds a central part of the outer structure, so that the central part covered by the gate structure becomes a channel region, and the outer structure at both sides of the central part respectively becomes a source region and a drain region.

公开(公告)号：US20230207669A1

公开(公告)日：2023-06-29

申请号：US18118154

申请日：2023-03-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Fu Chang ,  Kuan-Hung Chen ,  Guang-Yu Lo ,  Chun-Chia Chen ,  Chun-Tsen Lu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/66795 ,  H01L29/785 ,  H01L29/7834 ,  H01L29/511 ,  H01L21/022 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/28202

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

公开(公告)号：US11631753B2

公开(公告)日：2023-04-18

申请号：US16282323

申请日：2019-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Fu Chang ,  Kuan-Hung Chen ,  Guang-Yu Lo ,  Chun-Chia Chen ,  Chun-Tsen Lu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

公开(公告)号：US20200235227A1

公开(公告)日：2020-07-23

申请号：US16282323

申请日：2019-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Fu Chang ,  Kuan-Hung Chen ,  Guang-Yu Lo ,  Chun-Chia Chen ,  Chun-Tsen Lu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L21/02 ,  H01L29/51

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

公开(公告)号：US10403715B2

公开(公告)日：2019-09-03

申请号：US16222709

申请日：2018-12-17

Applicant: United Microelectronics Corp.

Inventor： Rung-Yuan Lee ,  Chun-Tsen Lu ,  Kuan-Hung Chen

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/41 ,  H01L29/417 ,  H01L23/535 ,  H01L21/306 ,  H01L29/66 ,  H01L21/308 ,  H01L29/786 ,  H01L21/84 ,  H01L27/12

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a semiconductor nanowire, a gate structure, a first metal nanowire and a second metal nanowire. The semiconductor nanowire is disposed vertically on the substrate. The gate structure surrounds a middle portion of the semiconductor nanowire. The first metal nanowire is located on a side of the semiconductor nanowire and is electronically connected to a lower portion of the semiconductor nanowire. The second metal nanowire is located on the other side of the semiconductor nanowire and is electronically connected to the gate structure.

公开(公告)号：US10043807B1

公开(公告)日：2018-08-07

申请号：US15641236

申请日：2017-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rung-Yuan Lee ,  Yu-Cheng Tung ,  Chun-Tsen Lu ,  En-Chiuan Liou ,  Kuan-Hung Chen

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L27/092 ,  H01L27/02 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a plural fin structures, two gates, a protection layer and an interlayer dielectric layer. The fin structures are disposed on a substrate. The two gates are disposed on the substrate across the fin structures. The protection layer is disposed on the substrate, surrounded sidewalls of the two gates. The interlayer dielectric layer is disposed on the substrate, covering the fin structures and the two gates.