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公开(公告)号:US20230082878A1
公开(公告)日:2023-03-16
申请号:US17502026
申请日:2021-10-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: BO TAO , Li Wang , Ching-Yang Wen , Purakh Raj Verma , ZHIBIAO ZHOU , DONG YIN , Gang Ren , Jian Xie
IPC: H01L27/12 , H01L23/525 , H01L27/112 , G11C17/16
Abstract: A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.
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公开(公告)号:US11923373B2
公开(公告)日:2024-03-05
申请号:US17502026
申请日:2021-10-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Bo Tao , Li Wang , Ching-Yang Wen , Purakh Raj Verma , Zhibiao Zhou , Dong Yin , Gang Ren , Jian Xie
IPC: H01L27/12 , G11C17/16 , H01L23/525 , H10B20/20 , H10B20/25
CPC classification number: H01L27/1207 , G11C17/16 , G11C17/165 , H01L23/5252 , H10B20/20 , H10B20/25
Abstract: A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.
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公开(公告)号:US20240170490A1
公开(公告)日:2024-05-23
申请号:US18424888
申请日:2024-01-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: BO TAO , Li Wang , Ching-Yang Wen , Purakh Raj Verma , Zhibiao Zhou , Dong Yin , Gang Ren , Jian Xie
IPC: H01L27/12 , G11C17/16 , H01L23/525 , H10B20/20 , H10B20/25
CPC classification number: H01L27/1207 , G11C17/16 , G11C17/165 , H01L23/5252 , H10B20/20 , H10B20/25
Abstract: A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.