公开(公告)号：US20200035544A1

公开(公告)日：2020-01-30

申请号：US16594188

申请日：2019-10-07

Applicant: SunEdison Semiconductor Limited (UEN201334164H)

Inventor： Henry Frank Erk ,  Sasha Kweskin ,  Jeffrey L. Libbert ,  Mayank Bulsara

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065

Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a multilayer dielectric layer.

公开(公告)号：US10269617B2

公开(公告)日：2019-04-23

申请号：US15623519

申请日：2017-06-15

Applicant: SunEdison Semiconductor Limited (UEN201334164H)

Inventor： Igor Peidous ,  Jeffrey L. Libbert

IPC: H01L21/762 ,  H01L21/304 ,  H01L21/02 ,  H01L21/761 ,  H01L29/06 ,  H01L21/322 ,  H01L21/265

Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

公开(公告)号：US20170243781A1

公开(公告)日：2017-08-24

申请号：US15435428

申请日：2017-02-17

Applicant: SunEdison Semiconductor Limited (UEN201334164H)

Inventor： Igor Peidous ,  Andrew M. Jones ,  Srikanth Kommu ,  Jeffrey L. Libbert

IPC: H01L21/762 ,  H01L29/40 ,  H01L21/265 ,  H01L21/28 ,  H01L21/18 ,  H01L29/04 ,  H01L29/30

CPC classification number: H01L21/76251 ,  H01L21/187 ,  H01L21/26506 ,  H01L21/28282 ,  H01L21/76254 ,  H01L29/045 ,  H01L29/30 ,  H01L29/408

Abstract: A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

公开(公告)号：US09159596B2

公开(公告)日：2015-10-13

申请号：US13663073

申请日：2012-10-29

Applicant: SunEdison Semiconductor Limited

Inventor： Gregory A. Young ,  Jeffrey L. Libbert

IPC: B32B38/10 ,  H01L21/67 ,  B32B43/00

CPC classification number: B32B43/006 ,  B32B38/10 ,  C09J2205/302 ,  H01L21/67092 ,  H01L2221/68386 ,  H01L2221/6839 ,  Y10S156/93 ,  Y10S156/941 ,  Y10T156/1168 ,  Y10T156/1184 ,  Y10T156/1961 ,  Y10T156/1978 ,  Y10T225/10 ,  Y10T225/12 ,  Y10T225/357 ,  Y10T225/393

Abstract: Apparatus and methods for mechanically cleaving a bonded wafer structure are disclosed. The apparatus and methods involve clamps that grip the bonded wafer structure and are actuated to cause the bonded structure to cleave.

Abstract translation: 公开了用于机械地切割接合晶片结构的装置和方法。 该装置和方法涉及夹持键合晶片结构并被致动以使接合结构断裂的夹具。

公开(公告)号：US10475695B2

公开(公告)日：2019-11-12

申请号：US15899636

申请日：2018-02-20

Applicant: SunEdison Semiconductor Limited (UEN201334164H)

Inventor： Igor Peidous ,  Jeffrey L. Libbert

IPC: H01L21/762 ,  H01L21/304 ,  H01L21/02 ,  H01L21/761 ,  H01L29/06 ,  H01L21/322 ,  H01L21/265

Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

公开(公告)号：US20180233420A1

公开(公告)日：2018-08-16

申请号：US15893055

申请日：2018-02-09

Applicant: SunEdison Semiconductor Limited (UEN201334164H)

Inventor： Igor Rapoport ,  Srikanth Kommu ,  Igor Peidous ,  Gang Wang ,  Jeffrey L. Libbert

IPC: H01L21/66 ,  H01L23/66

CPC classification number: H01L22/14 ,  G01R31/2648 ,  H01L22/20 ,  H01L23/66 ,  H01L27/12

Abstract: Methods for assessing the quality of a semiconductor structure having a charge trapping layer to, for example, determine if the structure is suitable for use as a radiofrequency device are disclosed. Embodiments of the assessing method may involve measuring an electrostatic parameter at an initial state and at an excited state in which charge carriers are generated.

公开(公告)号：US20180114720A1

公开(公告)日：2018-04-26

申请号：US15727723

申请日：2017-10-09

Applicant: SunEdison Semiconductor Limited (UEN201334164H)

Inventor： Gang Wang ,  Jeffrey L. Libbert ,  Shawn George Thomas ,  Qingmin Liu

IPC: H01L21/762 ,  H01L27/12 ,  H01L21/02

Abstract: A multilayer semiconductor on insulator structure is provided in which the handle substrate and an epitaxial layer in interfacial contact with the handle substrate comprise electrically active dopants of opposite type. The epitaxial layer is depleted by the handle substrate free carriers, thereby resulting in a high apparent resistivity, which improves the function of the structure in RF devices.

公开(公告)号：US10468294B2

公开(公告)日：2019-11-05

申请号：US16077142

申请日：2017-01-31

Applicant: SUNEDISON SEMICONDUCTOR LIMITED ,  Igor Peidous

Inventor： Igor Peidous ,  Andrew M. Jones ,  Srikanth Kommu ,  Gang Wang ,  Jeffrey L. Libbert

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/30 ,  H01L21/46 ,  H01L29/04 ,  H01L31/036 ,  H01L21/762 ,  H01L21/02 ,  H01L21/28

Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and the front surface of the single crystal semiconductor handle substrate has a surface roughness of at least about 0.1 micrometers as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers. The composite structure further comprises a charge trapping layer in contact with the front surface, the charge trapping layer comprising poly crystalline silicon, the poly crystalline silicon comprising grains having a plurality of crystal orientations; a dielectric layer in contact with the charge trapping layer; and a single crystal semiconductor device layer in contact with the dielectric layer.

公开(公告)号：US10381260B2

公开(公告)日：2019-08-13

申请号：US15526798

申请日：2015-11-13

Applicant: SunEdison Semiconductor Limited (UEN201334164H)

Inventor： Igor Peidous ,  Jeffrey L. Libbert ,  Srikanth Kommu ,  Andrew M. Jones ,  Samuel Christopher Pratt ,  Horacio Josue Mendez ,  Leslie George Stanton ,  Michelle Rene Dickinson

IPC: H01L21/762 ,  H01L21/02

Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.

公开(公告)号：US20180277421A1

公开(公告)日：2018-09-27

申请号：US15984586

申请日：2018-05-21

Applicant: SunEdison Semiconductor Limited (UEN201334164H)

Inventor： Igor Peidous ,  Jeffrey L. Libbert ,  Srikanth Kommu ,  Andrew Marquis Jones ,  Samuel Christopher Pratt ,  Horacio Josue Mendez ,  Leslie George Stanton ,  Michelle Rene Dickinson

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76251 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/76254

Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.