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公开(公告)号：US10991410B2
公开(公告)日：2021-04-27
申请号：US16598568
申请日：2019-10-10
Applicant: Spin Memory, Inc.
Inventor： Neal Berger , Benjamin Louie , Kadriye Deniz Bozdag
IPC: G11C11/16 , G06F12/0855 , H01L25/065
Abstract: A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank and writing a second plurality of data words and associated memory addresses into an error buffer. The method also comprises monitoring a first counter value which tracks a number of write 1 errors and a second counter value which tracks a number of write 0 errors in the memory bank. Further, the method comprises determining if the first counter value and the second counter value have exceeded a predetermined threshold. Responsive to a determination that the first counter value has exceeded the predetermined threshold increasing a write 1 voltage of the memory bank, and, further, responsive to a determination that the second counter value has exceeded the predetermined threshold increasing a write 0 voltage of the memory bank.
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2.发明申请
公开(公告)号：US20200302983A1
公开(公告)日：2020-09-24
申请号：US16362329
申请日：2019-03-22
Applicant: Spin Memory, Inc.
Inventor： Kuk-Hwan Kim , Kadriye Deniz Bozdag , Eric Michael Ryan
Abstract: A magnetic memory device that includes magnetic read elements and magnetic reference cells. The magnetic reference cells include magnetic tunnel junction elements having the same construction as the magnetic read elements. The reference cells produce a reference signal that can be compared with a read signal from the magnetic read element to determine whether the read element is in a high or low resistance state. During creation of the reference signal, the current passes in such a way so that reference cells are forced to be in the right state while causing no disturbance to the reference cell. The reference cell includes magnetic tunnel junction elements and also includes circuitry configured to produce a magnetic field that biases the magnetic tunnel junction elements of the reference cell into a desired magnetic state to ensure that the desired magnetic state of the reference cell magnetic tunnel junction elements is maintained.
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3.发明授权
公开(公告)号：US10580827B1
公开(公告)日：2020-03-03
申请号：US16192972
申请日：2018-11-16
Applicant: Spin Memory, Inc.
Inventor： Steven Watts , Georg Martin Wolf , Kadriye Deniz Bozdag , Bartlomiej Kardasz , Mustafa Pinarbasi
Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. The MRAM bit cell consists of a magnetic tunnel junction stack having a significantly improved performance of the magnetic storage layer. The MRAM device utilizes a polarizer layer with a magnetic vector that can switch between a stabilizing magnetic direction and a programming magnetic direction.
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公开(公告)号：US20200013827A1
公开(公告)日：2020-01-09
申请号：US16237171
申请日：2018-12-31
Applicant: Spin Memory, Inc.
Inventor： Kuk-Hwan Kim , Dafna Beery , Marcin Gajek , Michail Tzoufras , Kadriye Deniz Bozdag , Eric Michael Ryan , Satoru Araki , Andrew J. Walker
Abstract: A method for forming three-dimensional magnetic memory arrays by forming crystalized silicon structures from amorphous structures in the magnetic memory array, wherein the temperature needed to crystalize the amorphous silicon is lower than the temperature budget of the memory element so as to avoid damage to the memory element. An amorphous silicon is deposited, followed by a layer of Ti or Co. An annealing process is then performed which causes the Ti or Co to form TiSi2 or CoSi2 and also causes the underlying amorphous silicon to crystallize.
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公开(公告)号：US11094359B2
公开(公告)日：2021-08-17
申请号：US16256766
申请日：2019-01-24
Applicant: Spin Memory, Inc.
Inventor： Kadriye Deniz Bozdag , Mustafa Pinarbasi
Abstract: A magnetic memory pillar structure having a plurality of magnetic memory elements connected in series, wherein switching of individual memory elements in the pillar structure can be accomplished based on differing switching current values of the magnetic memory elements. Each of the plurality of memory elements advantageously have similar retention values in spite of the different switching current values (latency values) as a result of a precessional spin current injection structure provided in the memory element or memory elements having the lower switching current value.
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公开(公告)号：US10559338B2
公开(公告)日：2020-02-11
申请号：US16028412
申请日：2018-07-06
Applicant: SPIN MEMORY, Inc.
Inventor： Michail Tzoufras , Marcin Gajek , Kadriye Deniz Bozdag , Mourad El Baraji
Abstract: Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to program the state of a corresponding one of N cell elements of the MBC to a respective state parameter value. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.
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公开(公告)号：US20200243124A1
公开(公告)日：2020-07-30
申请号：US16256766
申请日：2019-01-24
Applicant: Spin Memory, Inc.
Inventor： Kadriye Deniz Bozdag , Mustafa Pinarbasi
Abstract: A magnetic memory pillar structure having a plurality of magnetic memory elements connected in series, wherein switching of individual memory elements in the pillar structure can be accomplished based on differing switching current values of the magnetic memory elements. Each of the plurality of memory elements advantageously have similar retention values in spite of the different switching current values (latency values) as a result of a precessional spin current injection structure provided in the memory element or memory elements having the lower switching current value.
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公开(公告)号：US20200212296A1
公开(公告)日：2020-07-02
申请号：US16236275
申请日：2018-12-28
Applicant: SPIN MEMORY, INC.
Inventor： Kuk-Hwan Kim , Dafna Beery , Marcin Gajek , Michail Tzoufras , Kadriye Deniz Bozdag , Eric Ryan , Satoru Araki , Andy Walker
IPC: H01L43/12 , H01L27/22 , H01L43/02 , H01L21/285 , H01L21/308 , H01L21/02
Abstract: Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.
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公开(公告)号：US20200013445A1
公开(公告)日：2020-01-09
申请号：US16028412
申请日：2018-07-06
Applicant: SPIN MEMORY, Inc.
Inventor： Michail Tzoufras , Marcin Gajek , Kadriye Deniz Bozdag , Mourad El Baraji
Abstract: Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to program the state of a corresponding one of N cell elements of the MBC to a respective state parameter value. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.
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公开(公告)号：US10326073B1
公开(公告)日：2019-06-18
申请号：US15858808
申请日：2017-12-29
Applicant: Spin Memory, Inc.
Inventor： Michail Tzoufras , Marcin Gajek , Kadriye Deniz Bozdag , Eric Michael Ryan
CPC classification number: H01L43/02 , G11C11/161 , H01L27/222 , H01L43/06 , H01L43/12 , H01L43/14
Abstract: The various implementations described herein include methods, devices, and systems for operating magnetic memory devices. In one aspect, a magnetic memory device includes: (1) a core; (2) a plurality of layers that surround the core in succession; (3) a first input terminal coupled to the core and configured to receive a first current, where: (a) the first current flows radially from the core through the plurality of layers; and (b) the radial flow of the first current imparts a torque on, at least, a magnetization of an inner layer of the plurality of layers; and (4) a second input terminal coupled to the core and configured to receive a second current, where: (i) the second current imparts a Spin Hall Effect (SHE) around a perimeter of the core; and (ii) the SHE contributes to the torque imparted on the magnetization of the inner layer by the first current.
