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公开(公告)号：US10530339B2
公开(公告)日：2020-01-07
申请号：US15435468
申请日：2017-02-17
Applicant: Schweitzer Engineering Laboratories, Inc.
Inventor： Srinivas Achanta
Abstract: A fixed latency configurable tap or fixed-tap digital filter may filter a signal in a fixed amount of time, regardless of the number of taps. The filter may include one or more of a clock, a plurality of registers in a shift register, an adder, an accumulator, and/or a scaler. In at least one embodiment, a running average may be maintained as samples are received such that the latency remains fixed with a constant number of clock cycles.
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公开(公告)号：US20160099803A1
公开(公告)日：2016-04-07
申请号：US14875453
申请日：2015-10-05
Applicant: Schweitzer Engineering Laboratories, Inc.
Inventor： Shankar V. Achanta , Srinivas Achanta , David E. Whitehead
IPC: H04L7/00
CPC classification number: H04J3/0638 , H04J3/0644 , H04L63/14
Abstract: The time signal verification and distribution device disclosed herein verifies and distributes a time signal to consuming devices. The device determines a time quality status of a first and second time signal, calculates a difference between a first and a second time signal, and compares the difference to a predetermined threshold. Based on the time quality status and the comparison, the time signal verification and distribution device distributes a time signal to a plurality of time signal consuming devices. Exceeding the predetermined threshold may indicate a spoofing attack or other problem with the time signals.
Abstract translation: 本文所公开的时间信号验证和分发装置验证并分配消耗装置的时间信号。 该装置确定第一和第二时间信号的时间质量状态，计算第一和第二时间信号之间的差异，并将差值与预定阈值进行比较。 基于时间质量状态和比较，时间信号验证和分发设备将时间信号分配给多个时间信号消耗设备。 超过预定阈值可以指示欺骗攻击或时间信号的其他问题。
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公开(公告)号：US09300591B2
公开(公告)日：2016-03-29
申请号：US14094211
申请日：2013-12-02
Applicant: Schweitzer Engineering Laboratories, Inc.
Inventor： Manodev J. Rajasekaran , David M. Rector , Damian Sanchez Moreno , M. Wesley Kunzler , Srinivas Achanta , Jerry J. Bennett , Ian C. Ender
IPC: H04L12/835 , H04L12/801 , H04L12/933
Abstract: Disclosed is a network communication switch that facilitates reliable communication of high priority traffic over lower priority traffic across all ingress and egress ports. The network communication switch may monitor the frame storage buffer regardless of egress port, and when the frame storage buffer reaches a predetermined level, the switch may discard lower priority frames from the most congested port. When the frame storage buffer reaches a second predetermined level, the switch may discard lower priority frames before they are stored according to egress port. The network communication switch may further monitor ingress frames for priority, and assign priority to frames according to pre-assigned priority, ingress port, and/or frame contents.
Abstract translation: 公开了一种网络通信交换机，其便于通过所有入口和出口端口的较低优先级业务的高优先级流量的可靠通信。 网络通信交换机可以监视帧存储缓冲器而不管出口端口，并且当帧存储缓冲器达到预定级别时，交换机可以丢弃来自最拥塞端口的较低优先级帧。 当帧存储缓冲器达到第二预定级别时，交换机可以在根据出口端口存储之前丢弃较低优先级的帧。 网络通信交换机可以进一步监控入口帧的优先级，并根据预分配的优先级，入口端口和/或帧内容来分配优先级。
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公开(公告)号：US20200028494A1
公开(公告)日：2020-01-23
申请号：US16587337
申请日：2019-09-30
Applicant: Schweitzer Engineering Laboratories, Inc.
Inventor： Srinivas Achanta
IPC: H03H17/02
Abstract: A fixed latency configurable tap or fixed-tap digital filter may filter a signal in a fixed amount of time, regardless of the number of taps. The filter may include one or more of a clock, a plurality of registers in a shift register, an adder, an accumulator, and/or a scaler. In at least one embodiment, a running average may be maintained as samples are received such that the latency remains fixed with a constant number of clock cycles.
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公开(公告)号：US20150043697A1
公开(公告)日：2015-02-12
申请号：US13964786
申请日：2013-08-12
Applicant: Schweitzer Engineering Laboratories, Inc.
Inventor： Srinivas Achanta , Hidayatullah Ahsan
CPC classification number: H04J3/0638 , H02J13/00 , H04B3/04 , H04J3/065 , H04J3/0667 , H04J3/0697 , Y02E60/74 , Y04S10/30
Abstract: The present application discloses a time distribution device capable of providing a synchronized time signal to a plurality of end devices connected to the time distribution device with cables of various lengths. The time distribution device may receive a time signal, generate a time reference based on the received time signal, compensate the time reference for hardware delay, and overcompensate the time reference for a delay caused by a maximum cable length. Prior to being distributed to various end devices, each being connected with the time distribution device by cables of varying length, this overcompensated time reference may then be delayed by an amount based on the cable length connecting each respective end device such that the arrival of each of the synchronized time references at the various end devices is synchronized.
Abstract translation: 本申请公开了一种能够向具有不同长度的电缆连接到时间分配装置的多个终端装置提供同步时间信号的时间分配装置。 时间分配装置可以接收时间信号，基于接收的时间信号产生时间参考，补偿硬件延迟的时间参考，并且对由最大电缆长度引起的延迟的时间基准进行过补偿。 在分配给各种终端设备之前，每个终端设备通过长度不同的电缆与时间分配设备连接，然后可以基于连接每个相应终端设备的电缆长度将该过度补偿的时间基准延迟一定量，使得每个终端设备的到达 在各种终端设备的同步时间基准是同步的。
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Patent Agency Ranking
公开(公告)号：US11057021B2
公开(公告)日：2021-07-06
申请号：US16587337
申请日：2019-09-30
Applicant: Schweitzer Engineering Laboratories, Inc.
Inventor： Srinivas Achanta
Abstract: A fixed latency configurable tap or fixed-tap digital filter may filter a signal in a fixed amount of time, regardless of the number of taps. The filter may include one or more of a clock, a plurality of registers in a shift register, an adder, an accumulator, and/or a scaler. In at least one embodiment, a running average may be maintained as samples are received such that the latency remains fixed with a constant number of clock cycles.
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公开(公告)号：US20180238956A1
公开(公告)日：2018-08-23
申请号：US15435468
申请日：2017-02-17
Applicant: Schweitzer Engineering Laboratories, Inc.
Inventor： Srinivas Achanta
IPC: G01R31/08 , G01R31/02 , G01R19/257
CPC classification number: H03H17/026
Abstract: A fixed latency configurable tap or fixed-tap digital filter may filter a signal in a fixed amount of time, regardless of the number of taps. The filter may include one or more of a clock, a plurality of registers in a shift register, an adder, an accumulator, and/or a scaler. In at least one embodiment, a running average may be maintained as samples are received such that the latency remains fixed with a constant number of clock cycles.
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公开(公告)号：US09270442B2
公开(公告)日：2016-02-23
申请号：US14264394
申请日：2014-04-29
Applicant: Schweitzer Engineering Laboratories, Inc.
Inventor： Raymond W. Rice , Srinivas Achanta
IPC: H04L7/00
CPC classification number: H04L7/0041 , H04J3/0635 , H04J3/0682
Abstract: Disclosed herein are a variety of systems and methods for correcting for propagation delay in time signals used in connection with an electric power generation and delivery system. According to various embodiments, a device consistent with the present disclosure may determine an estimated propagation delay between an accurate time source and a receiving device. The propagation delay may be determined based on a variety of transmission parameters including, for example, communication channel type and/or length. A corrected time signal may be generated by advancing a reference incitation such as an “on-time” reference and/or “start-of-second” reference included in the time signal by an amount associated with the propagation delay. The corrected time signal may then be transmitted to the receiving device.
Abstract translation: 这里公开了用于校正与发电和输送系统相关联的时间信号中的传播延迟的各种系统和方法。 根据各种实施例，与本公开一致的设备可以确定精确时间源和接收设备之间的估计的传播延迟。 可以基于包括例如通信信道类型和/或长度的各种传输参数来确定传播延迟。 可以通过将包括在时间信号中的诸如“准时”参考和/或“起始”参考的参考煽动与传播延迟相关联的量来产生校正的时间信号。 然后可以将校正的时间信号发送到接收装置。
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公开(公告)号：US09813173B2
公开(公告)日：2017-11-07
申请号：US14875453
申请日：2015-10-05
Applicant: Schweitzer Engineering Laboratories, Inc.
Inventor： Shankar V. Achanta , Srinivas Achanta , David E. Whitehead
CPC classification number: H04J3/0638 , H04J3/0644 , H04L63/14
Abstract: The time signal verification and distribution device disclosed herein verifies and distributes a time signal to consuming devices. The device determines a time quality status of a first and second time signal, calculates a difference between a first and a second time signal, and compares the difference to a predetermined threshold. Based on the time quality status and the comparison, the time signal verification and distribution device distributes a time signal to a plurality of time signal consuming devices. Exceeding the predetermined threshold may indicate a spoofing attack or other problem with the time signals.
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公开(公告)号：US09319100B2
公开(公告)日：2016-04-19
申请号：US13964786
申请日：2013-08-12
Applicant: Schweitzer Engineering Laboratories, Inc.
Inventor： Srinivas Achanta , Hidayatullah Ahsan
CPC classification number: H04J3/0638 , H02J13/00 , H04B3/04 , H04J3/065 , H04J3/0667 , H04J3/0697 , Y02E60/74 , Y04S10/30
Abstract: The present application discloses a time distribution device capable of providing a synchronized time signal to a plurality of end devices connected to the time distribution device with cables of various lengths. The time distribution device may receive a time signal, generate a time reference based on the received time signal, compensate the time reference for hardware delay, and overcompensate the time reference for a delay caused by a maximum cable length. Prior to being distributed to various end devices, each being connected with the time distribution device by cables of varying length, this overcompensated time reference may then be delayed by an amount based on the cable length connecting each respective end device such that the arrival of each of the synchronized time references at the various end devices is synchronized.
Abstract translation: 本申请公开了一种能够向具有不同长度的电缆连接到时间分配装置的多个终端装置提供同步时间信号的时间分配装置。 时间分配装置可以接收时间信号，基于接收的时间信号产生时间参考，补偿硬件延迟的时间参考，并且对由最大电缆长度引起的延迟的时间基准进行过补偿。 在分配给各种终端设备之前，每个终端设备通过长度不同的电缆与时间分配设备连接，然后可以基于连接每个相应终端设备的电缆长度将该过度补偿的时间基准延迟一定量，使得每个终端设备的到达 在各种终端设备的同步时间基准是同步的。
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