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1.发明公开公开(公告)号：US20240324234A1
公开(公告)日：2024-09-26
申请号：US18430291
申请日：2024-02-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeonil Lee , Kyunghwan Lee , Youngin Goh , Yukio Hayakawa
Abstract: A 3D FeRAM is provided. The 3D FeRAM includes a semiconductor patterns stacked in a vertical direction on a substrate and spaced apart from each other in a first horizontal direction, bit lines on first side surface of the semiconductor patterns, extending in the first horizontal direction, and spaced apart from each other in the vertical direction, first electrodes on second side surfaces of the semiconductor patterns and spaced apart from each other in both the vertical direction and the first horizontal direction, a ferroelectric layer on the first electrodes, second electrodes on the ferroelectric layers, extending in the first horizontal direction, and spaced apart from each other in the vertical direction, and word lines between two adjacent semiconductor patterns extending in the vertical direction.
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公开(公告)号：US20240015978A1
公开(公告)日：2024-01-11
申请号：US18320816
申请日：2023-05-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Siyeon Cho , Taeyoung Kim , Hyunmog Park , Bongyong Lee , Yukio Hayakawa
IPC: H10B51/20 , H10B51/10 , H01L23/528
CPC classification number: H10B51/20 , H10B51/10 , H01L23/5283
Abstract: Disclosed are semiconductor memory devices and electronic systems including the same. The semiconductor memory device may include a vertical channel perpendicular to a top surface of a substrate, word lines disposed on a first side of the vertical channel and vertically stacked on the substrate, back-gate electrodes disposed on a second side of the vertical channel and vertically stacked on the substrate, a ferroelectric layer disposed between the word lines and the first side of the vertical channel, a first intermediate insulating layer disposed between the ferroelectric layer and the first side of the vertical channel, and a second intermediate insulating layer disposed between the back-gate electrodes and the second side of the vertical channel.
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公开(公告)号：US11957071B2
公开(公告)日：2024-04-09
申请号：US17749289
申请日：2022-05-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yukio Hayakawa , Jooheon Kang , Myunghun Woo , Gunwook Yoon , Doohee Hwang
CPC classification number: H10N70/826 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/0069 , H10B63/34 , H10N70/841 , H10N70/8833
Abstract: A vertical variable resistance memory device includes gate electrodes and a pillar structure. The gate electrodes are spaced apart from one another on a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate. The pillar structure extends in the vertical direction through the gate electrodes on the substrate. The pillar structure includes a vertical gate electrode extending in the vertical direction, a variable resistance pattern disposed on a sidewall of the vertical gate electrode, and a channel disposed on an outer sidewall of the variable resistance pattern. The channel and the vertical gate electrode contact each other.
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公开(公告)号：US20230269941A1
公开(公告)日：2023-08-24
申请号：US18095576
申请日：2023-01-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Bongyong Lee , Yukio Hayakawa , Taeyoung Kim , Hyunmog Park , Siyeon Cho
CPC classification number: H10B43/27 , H10B43/35 , H10B43/10 , H10B41/10 , H10B41/27 , H10B41/35 , G11C16/14
Abstract: A semiconductor device includes a source structure, gate electrodes spaced apart from each other and stacked in a first direction, perpendicular to an upper surface of the source structure, and a channel structure extending through the gate electrodes in the first direction, and including a dielectric layer, a charge storage layer, a tunneling layer, a channel layer, and a buried semiconductor layer. The dielectric layer is between the gate electrodes and the charge storage layer. The tunneling layer is between charge storage layer and the channel layer. The channel layer is between the tunneling layer and the buried semiconductor layer. An outer surface of a lower portion of the channel layer is in contact with the source structure, and the dielectric layer includes a ferroelectric material, the channel layer includes an oxide semiconductor material, and the buried semiconductor layer includes silicon (Si).
