-
公开(公告)号：US12135679B2
公开(公告)日：2024-11-05
申请号：US17835746
申请日：2022-06-08
Applicant: STMicroelectronics S.r.l.
Inventor： Antonino Mondello , Salvatore Pisasale
IPC: G06F15/78 , G06F15/173
Abstract: In an embodiment a system on chip includes at least one master device, at least one slave device, a connection interface configured to route signals between the at least one master device and the at least one slave device, the connection interface configured to operate according to configuration parameters, and a configuration bus connected to the connection interface, wherein the configuration bus is configured to deliver new configuration parameters to the connection interface so as to adapt operation of the connection interface.
-
2.发明授权公开(公告)号：US12045339B2
公开(公告)日：2024-07-23
申请号：US17469234
申请日：2021-09-08
Applicant: STMicroelectronics S.r.l.
Inventor： Antonino Mondello , Alessandro Inglese
CPC classification number: G06F21/55 , G06F1/26 , G06F2221/034
Abstract: In an embodiment a system on chip includes a persistent power supply and anti-replay mechanism comprising a monotonic counter including a volatile counter register powered by the persistent power supply.
-
公开(公告)号：US20230318590A1
公开(公告)日：2023-10-05
申请号：US18187379
申请日：2023-03-21
Applicant: STMicroelectronics S.r.l.
Inventor： Riccardo Condorelli , Michele Alessandro Carrano , Antonino Mondello
Abstract: In accordance with an embodiment, a method includes: producing a set of delayed replicas of a reference clock signal, wherein delayed replicas in the set of delayed replicas have respective signal edges delayed in time by a mutual time delay therebetween; producing a set of edge detecting signals comprising edge detecting signals indicative of respective distances of edges of delayed replicas in the set of delayed replicas from an edge of a clock signal having a clock period; selecting based on edge detecting signals in the set of edge detecting signals a delayed replica in the set of delayed replicas having a distance from the clock signal edge that is shorter than the distance from the clock signal edge of any other delayed replica in the set of delayed replicas.
-
Patent Agency Ranking
4.发明申请公开(公告)号：US20220100848A1
公开(公告)日：2022-03-31
申请号：US17469234
申请日：2021-09-08
Applicant: STMicroelectronics S.r.l.
Inventor： Antonino Mondello , Alessandro Inglese
Abstract: In an embodiment a system on chip includes a persistent power supply and anti-replay mechanism comprising a monotonic counter including a volatile counter register powered by the persistent power supply.
-
公开(公告)号：US12197557B2
公开(公告)日：2025-01-14
申请号：US17454231
申请日：2021-11-09
Inventor： Antonino Mondello , Stefano Catalano , Cyril Pascal
Abstract: According to one aspect, a system-on-a-chip is proposed which includes a memory storage, a computation circuit, a comparison circuit, and a validation circuit. The memory storage is configured to store an external software module. The computation circuit is configured to compute several modified software modules from the external software module and compute check values by iteration until obtaining a final check value. Each check value is computed at least from a given modified software module and a check value previously computed, starting with a predefined initial check value. The comparison circuit is configured to compare the final check value to an expected value stored in the system-on-a-chip. The validation circuit is configured to validate the external software module when the final check value is equal to the expected value.
-
公开(公告)号：US12132815B2
公开(公告)日：2024-10-29
申请号：US18174183
申请日：2023-02-24
Applicant: STMicroelectronics S.r.l.
Inventor： Riccardo Condorelli , Antonino Mondello , Michele Alessandro Carrano
Abstract: A method includes providing a reference clock signal having a reference period, providing a sampling clock signal having a sampling clock period shorter than the reference period of the reference clock signal, measuring the first subperiod as a first ratio of the first subperiod to the period of the sampling clock signal, measuring the second subperiod as a second ratio of the second subperiod to the period of the sampling clock signal, detecting a starting edge of a clock signal having a clock period greater than the reference period, producing a reconstructed reference signal based on the first ratio, the second ratio, and the detected starting edge, comparing the clock period of the clock signal with a period of the reconstructed reference signal to obtain a differential signal indicating a difference therebetween, and providing the differential signal to user circuitry for calibrating the clock signal.
-
公开(公告)号：US12107584B2
公开(公告)日：2024-10-01
申请号：US18187379
申请日：2023-03-21
Applicant: STMicroelectronics S.r.l.
Inventor： Riccardo Condorelli , Michele Alessandro Carrano , Antonino Mondello
Abstract: In accordance with an embodiment, a method includes: producing a set of delayed replicas of a reference clock signal, wherein delayed replicas in the set of delayed replicas have respective signal edges delayed in time by a mutual time delay therebetween; producing a set of edge detecting signals comprising edge detecting signals indicative of respective distances of edges of delayed replicas in the set of delayed replicas from an edge of a clock signal having a clock period; selecting based on edge detecting signals in the set of edge detecting signals a delayed replica in the set of delayed replicas having a distance from the clock signal edge that is shorter than the distance from the clock signal edge of any other delayed replica in the set of delayed replicas.
-
公开(公告)号：US20220197990A1
公开(公告)日：2022-06-23
申请号：US17454231
申请日：2021-11-09
Applicant: STMicroelectronics S.r.l.
Inventor： Antonino Mondello , Stefano Catalano , Cyril Pascal
Abstract: According to one aspect, a system-on-a-chip is proposed which includes a memory storage, a computation circuit, a comparison circuit, and a validation circuit. The memory storage is configured to store an external software module. The computation circuit is configured to compute several modified software modules from the external software module and compute check values by iteration until obtaining a final check value. Each check value is computed at least from a given modified software module and a check value previously computed, starting with a predefined initial check value. The comparison circuit is configured to compare the final check value to an expected value stored in the system-on-a-chip. The validation circuit is configured to validate the external software module when the final check value is equal to the expected value.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.034 seconds)
