公开(公告)号：US11328755B2

公开(公告)日：2022-05-10

申请号：US16839329

申请日：2020-04-03

Applicant: Silicon Laboratories Inc.

Inventor： Arjun Singhal ,  Subrata Roy

IPC: G06F1/12 ,  G11C7/22 ,  G06F1/3234 ,  G11C7/10 ,  G06F3/06

Abstract: A data producer stores input data in a buffer in response to a slow clock signal and provides read data from the buffer in response to a read pointer signal. A data movement circuit reads the input data from the buffer using the read pointer signal and provides an update read pointer signal in response to reading the input data. The data movement circuit operates in response to a fast clock signal, and includes a metastable-free synchronizer circuit having inputs for receiving the update read pointer signal, the slow clock signal, and the read pointer signal, and an output for providing a synchronized read pointer signal equal to the read pointer signal except between a change in the read pointer signal while the slow clock signal is active until an inactivation of the slow clock signal. The buffer provides the read data in response to the synchronized read pointer signal.

公开(公告)号：US08762586B2

公开(公告)日：2014-06-24

申请号：US13799159

申请日：2013-03-13

Applicant: Silicon Laboratories Inc.

Inventor： Clayton Daigle ,  Jinwen Xiao ,  Axel Thomsen ,  Subrata Roy ,  Xiaodong Wang

IPC: G06F3/00 ,  G06F13/00

CPC classification number: H03K19/017509

Abstract: An integrated circuit (IC) includes a plurality of pads adapted to communicate signals with a circuit external to the IC, and a first mixed signal interface block coupled to a first pad in the plurality of pads, where the first mixed signal interface block is adapted to receive a first trigger signal from the circuit external to the IC and to provide a second trigger signal. The IC further includes a second mixed signal interface block coupled to a second pad in the plurality of pads, where the second mixed signal interface block is adapted to receive and track a first input signal from the circuit external to the IC in a first mode of operation of the IC. The second mixed signal interface block is further adapted to generate, in response to the second trigger signal, a first output signal based on the first input signal and to provide the first output signal to a digital core of the IC in a second mode of operation of the IC, where the power consumption of the IC is lower in the first mode of operation than in the second mode of operation.

Abstract translation: 集成电路（IC）包括适于与IC外部的电路传送信号的多个焊盘以及耦合到多个焊盘中的第一焊盘的第一混合信号接口块，其中第一混合信号接口块被适配 以从IC外部的电路接收第一触发信号并提供第二触发信号。 IC还包括耦合到多个焊盘中的第二焊盘的第二混合信号接口块，其中第二混合信号接口块适于以第一模式的第一模式接收并跟踪来自IC外部的电路的第一输入信号 IC的运作。 第二混合信号接口块还适于响应于第二触发信号而产生基于第一输入信号的第一输出信号，并且在第二操作模式中将第一输出信号提供给IC的数字核心 的IC，其中IC的功耗在第一操作模式中比在第二操作模式中更低。

公开(公告)号：US20240393857A1

公开(公告)日：2024-11-28

申请号：US18321058

申请日：2023-05-22

Applicant: Silicon Laboratories Inc.

Inventor： Subrata Roy

IPC: G06F1/324 ,  G06F1/08 ,  G06F1/14

Abstract: A method updates a low frequency count value at a first frequency in an active mode and maintains the low frequency count value in the low power mode. Updating the low frequency count value includes updating a fractional counter in response to a first clock signal, updating an integral counter in response to a second clock signal, and generating the second clock signal based on the fractional count and the first clock signal. The first clock signal has a second frequency. The first frequency is lower than the second frequency. Updating the low frequency count value may include adjusting the low frequency count value in response to exiting the low power mode based on a difference between a current value of a real time clock counter and a prior value of the real time clock counter stored upon entry into the low power mode.

公开(公告)号：US20210312962A1

公开(公告)日：2021-10-07

申请号：US16839329

申请日：2020-04-03

Applicant: Silicon Laboratories Inc.

Inventor： Arjun Singhal ,  Subrata Roy

IPC: G11C7/22 ,  G11C7/10 ,  G06F1/3234

Abstract: A data producer stores input data in a buffer in response to a slow clock signal and provides read data from the buffer in response to a read pointer signal. A data movement circuit reads the input data from the buffer using the read pointer signal and provides an update read pointer signal in response to reading the input data. The data movement circuit operates in response to a fast clock signal, and includes a metastable-free synchronizer circuit having inputs for receiving the update read pointer signal, the slow clock signal, and the read pointer signal, and an output for providing a synchronized read pointer signal equal to the read pointer signal except between a change in the read pointer signal while the slow clock signal is active until an inactivation of the slow clock signal. The buffer provides the read data in response to the synchronized read pointer signal.

公开(公告)号：US20150220466A1

公开(公告)日：2015-08-06

申请号：US14169503

申请日：2014-01-31

Applicant: Silicon Laboratories Inc.

Inventor： Subrata Roy

IPC: G06F13/28 ,  G06F13/364 ,  G06F13/38

CPC classification number: G06F13/28 ,  G06F13/364

Abstract: A method includes assigning a plurality of pads of an integrated circuit (IC) to a direct memory access (DMA) channel of the IC; and storing DMA requests associated with the pads in a queue such that at a given time, the queue stores data indicative of DMA requests that are associated with more than one pad.

Abstract translation: 一种方法包括将集成电路（IC）的多个焊盘分配给IC的直接存储器访问（DMA）通道; 以及将与所述焊盘相关联的DMA请求存储在队列中，使得在给定时间，所述队列存储指示与多于一个焊盘相关联的DMA请求的数据。

公开(公告)号：US20140002133A1

公开(公告)日：2014-01-02

申请号：US13799159

申请日：2013-03-13

Applicant: SILICON LABORATORIES INC.

Inventor： Clayton Daigle ,  Jinwen Xiao ,  Axel Thomsen ,  Subrata Roy ,  Xiaodong Wang

IPC: H03K19/0175

CPC classification number: H03K19/017509

Abstract: An integrated circuit (IC) includes a plurality of pads adapted to communicate signals with a circuit external to the IC, and a first mixed signal interface block coupled to a first pad in the plurality of pads, where the first mixed signal interface block is adapted to receive a first trigger signal from the circuit external to the IC and to provide a second trigger signal. The IC further includes a second mixed signal interface block coupled to a second pad in the plurality of pads, where the second mixed signal interface block is adapted to receive and track a first input signal from the circuit external to the IC in a first mode of operation of the IC. The second mixed signal interface block is further adapted to generate, in response to the second trigger signal, a first output signal based on the first input signal and to provide the first output signal to a digital core of the IC in a second mode of operation of the IC, where the power consumption of the IC is lower in the first mode of operation than in the second mode of operation.

Abstract translation: 集成电路（IC）包括适于与IC外部的电路传送信号的多个焊盘以及耦合到多个焊盘中的第一焊盘的第一混合信号接口块，其中第一混合信号接口块被适配 以从IC外部的电路接收第一触发信号并提供第二触发信号。 IC还包括耦合到多个焊盘中的第二焊盘的第二混合信号接口块，其中第二混合信号接口块适于以第一模式的第一模式接收并跟踪来自IC外部的电路的第一输入信号 IC的运作。 第二混合信号接口块还适于响应于第二触发信号而产生基于第一输入信号的第一输出信号，并且在第二操作模式中将第一输出信号提供给IC的数字核心 的IC，其中IC的功耗在第一操作模式中比在第二操作模式中更低。

公开(公告)号：US09390037B2

公开(公告)日：2016-07-12

申请号：US14169503

申请日：2014-01-31

Applicant: Silicon Laboratories Inc.

Inventor： Subrata Roy

IPC: G06F13/28 ,  G06F13/38 ,  G06F13/364

CPC classification number: G06F13/28 ,  G06F13/364

Abstract: A method includes assigning a plurality of pads of an integrated circuit (IC) to a direct memory access (DMA) channel of the IC; and storing DMA requests associated with the pads in a queue such that at a given time, the queue stores data indicative of DMA requests that are associated with more than one pad.

Abstract translation: 一种方法包括将集成电路（IC）的多个焊盘分配给IC的直接存储器访问（DMA）通道; 以及将与所述焊盘相关联的DMA请求存储在队列中，使得在给定时间，所述队列存储指示与多于一个焊盘相关联的DMA请求的数据。