公开(公告)号：US20230028092A1

公开(公告)日：2023-01-26

申请号：US17864689

申请日：2022-07-14

申请人： SEIKO EPSON CORPORATION

发明人： Daishi Kondo ,  Gaku Numano

IPC分类号： G09G3/36

摘要： A display driver includes a line latch circuit; a first D/A conversion circuit; a second D/A conversion circuit; a first amplifier circuit configured to initialize charges of a capacitor of a first switched capacitor circuit in a first initialization period and output a data voltage in a first output period; a second amplifier circuit configured to initialize charges of a capacitor of a second switched capacitor circuit in a second initialization period and output a data voltage in a second output period; and a control circuit. The control circuit is configured to end the second initialization period of the second amplifier circuit before display data is latched by the line latch circuit at a latch timing and an output of the first amplifier circuit changes.

公开(公告)号：US11615758B2

公开(公告)日：2023-03-28

申请号：US17864689

申请日：2022-07-14

申请人： SEIKO EPSON CORPORATION

发明人： Daishi Kondo ,  Gaku Numano

IPC分类号： G09G3/36

摘要： A display driver includes a line latch circuit; a first D/A conversion circuit; a second D/A conversion circuit; a first amplifier circuit configured to initialize charges of a capacitor of a first switched capacitor circuit in a first initialization period and output a data voltage in a first output period; a second amplifier circuit configured to initialize charges of a capacitor of a second switched capacitor circuit in a second initialization period and output a data voltage in a second output period; and a control circuit. The control circuit is configured to end the second initialization period of the second amplifier circuit before display data is latched by the line latch circuit at a latch timing and an output of the first amplifier circuit changes.

公开(公告)号：US11094241B2

公开(公告)日：2021-08-17

申请号：US16919183

申请日：2020-07-02

申请人： Seiko Epson Corporation

发明人： Daishi Kondo

IPC分类号： G09G5/00 ,  G09G3/20 ,  G02F1/137

摘要： A display driver (100) includes terminals (TSEG1 and TSEG2) and a drive circuit (130). The terminal (TSEG1) can be connected to a segment electrode (ESEG1). The terminal (TSEG2) can be connected to a segment electrode (ESEG2) whose area is larger than the area of the segment electrode (ESEG1). The drive circuit (130) outputs a PWM segment drive signal (SSEG1) to the terminal (ESEG1), and outputs a PWM segment drive signal (SSEG2) to the terminal (TSEG2). When the same effective voltage is applied to the segment electrode (ESEG1) and the segment electrode (ESEG2), the duty ratio of the segment drive signal (SSEG1) is smaller than the duty ratio of the segment drive signal (ESEG2).