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公开(公告)号：US12165734B2
公开(公告)日：2024-12-10
申请号：US17895642
申请日：2022-08-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minho Kim , Hyunmook Choi
Abstract: A nonvolatile memory device includes a memory cell region and a peripheral circuit region disposed below the memory cell region. The peripheral circuits include a page buffer, a row decoder, and other peripheral circuits, wherein the page buffer is included in a page buffer block disposed on a lower surface of the first semiconductor substrate to be distinguished from other circuits included in the peripheral circuit region in a first direction perpendicular to an upper surface of the first semiconductor substrate, is connected to the memory cell region through a connection portion penetrating through the first semiconductor substrate, and includes a plurality of vertical transistors each defined by a source region, a channel region, and a drain region stacked in sequence in the first direction.
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公开(公告)号：US20230118956A1
公开(公告)日：2023-04-20
申请号：US18047270
申请日：2022-10-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Younggul Song , Junyeong Seok , Eun chu OH , Minho Kim , Byungchul Jang
IPC: H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L23/522 , H01L23/528 , H01L27/11556 , H01L27/11565 , H01L27/1157 , G11C16/08
Abstract: A non-volatile memory device includes a substrate, a stack structure that includes a first gate layer that extends in a horizontal direction and a second gate layer that extends in the horizontal direction and is disposed apart from the first gate layer in a vertical direction, a plurality of first channel structures that penetrate in the vertical direction through a first channel region of the stack structure, a plurality of second channel structures that penetrate in the vertical direction through a second channel region of the stack structure, a first anti-fuse structure and a second anti-fuse structure that each penetrate in the vertical direction through an anti-fuse region of the stack structure, a first anti-fuse transistor that is electrically connected to the first gate layer through the first anti-fuse structure, and a second anti-fuse transistor that is electrically connected to the second gate layer through the second anti-fuse structure.
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公开(公告)号：US11455140B2
公开(公告)日：2022-09-27
申请号：US17261956
申请日：2019-05-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Doochan Hwang , Minho Kim , Jinjoo Chung , Namhyun Kim , Sunho Park , Joonyoung Lee
IPC: G06F3/14 , H04L65/401 , G06F9/451 , H04W4/80 , G06Q20/32
Abstract: Provided are an electronic device and a method of controlling an external device by the electronic device. According to various embodiments of the present disclosure, a method of controlling an external device by an electronic device includes displaying, on a screen, a first user interface (UI) corresponding to first UI data received from an external server, transmitting, to the external device, second UI data corresponding to the first UI, receiving, from the external device, coordinates selected by a user using the external device, obtaining additional information related to the first UI when the coordinates correspond to a position of the first UI displayed on the screen, and transmitting, to the external device, the additional information and an execution command of an application using the additional information.
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公开(公告)号：US11409193B2
公开(公告)日：2022-08-09
申请号：US17028049
申请日：2020-09-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Mankyu Kang , Hoon Kim , Jongkeun Oh , Minho Kim , Heebom Kim
Abstract: A reticle for an apparatus for EUV exposure and a method of manufacturing a reticle, the reticle including a substrate including an edge region and a main region; a multi-layer structure on the main region and the edge region, a sidewall of the multi-layer structure overlying the edge region; a capping layer covering an upper surface and the sidewall of the multi-layer structure and at least a portion of the edge region of the substrate; and an absorber layer on the capping layer, the absorber layer covering an entire upper surface of the capping layer on the edge region of the substrate, wherein a stacked structure of the capping layer and the absorber layer is on an upper surface of the edge region of the substrate, and a sidewall of the stacked structure of the capping layer and the absorber layer is perpendicular to an upper surface of the substrate.
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公开(公告)号：US11343914B2
公开(公告)日：2022-05-24
申请号：US16281702
申请日：2019-02-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wangik Son , Minho Kim , Sunghyun Kim , Eungwon Kim , Chanbeom Jeong
Abstract: An electronic device is provided. The electronic device includes a conductive support member, a first circuit board connected to the conductive support member by a first capacitor, a second circuit board connected to the conductive support member by a second capacitor, a first conductive connection member electrically connecting the first circuit board and the second circuit board, and a first ground structure, at least a portion of the first ground structure being interposed between the first conductive connection member and the conductive support member. The ground structure includes a non-conductive layer physically contacting the conductive support member, and a conductive layer electrically connected to the first conductive connection member to form a capacitive coupling with the conductive support member.
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6.发明授权
公开(公告)号：US10185408B2
公开(公告)日：2019-01-22
申请号：US14474813
申请日：2014-09-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaehak Lee , Dooyong Park , Younggyun Lee , Minho Kim , Gyucheol Choi
IPC: G06F3/0354 , G06F3/041 , G06F3/0488
Abstract: A method and a system for inputting in an electronic device are provided. The method includes receiving a proximity input provided by an input tool through a user interface, the input tool having a drawing means with a predetermined length which is within a distance of a proximity input supporting section of the electronic device, identifying an attribute of the received proximity input, determining a display attribute based on the identified attribute of the proximity input, and outputting a drawing on the user interface corresponding to the determined display attribute and a drawing pattern of the proximity input.
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公开(公告)号：US09860440B2
公开(公告)日：2018-01-02
申请号：US14990909
申请日：2016-01-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wooyong Lee , Kwangkyu Park , Minho Kim , Hyeonjae Bak
CPC classification number: H04N5/23219 , G06F1/3231 , H04N5/23241 , H04N5/23293
Abstract: A control for a power saving of an electronic device is disclosed. The device includes a camera configured to be activated and then obtain an image when no input event is received within a given time after activation of a selected function. The device further includes a control unit configured to, if the obtained image contains a specific pattern, determine whether the specific pattern corresponds to a human face pattern, and to, if the specific pattern does not correspond to the human face pattern, perform a power saving control of the electronic device.
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公开(公告)号：US09606665B2
公开(公告)日：2017-03-28
申请号：US14531303
申请日：2014-11-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunsuk Choi , Minho Kim , Jiwoong Oh
IPC: G06F3/0488 , G06F3/041 , G06F3/0481
CPC classification number: G06F3/0416 , G06F3/04817 , G06F3/04886 , G06F2203/04104
Abstract: A method of moving an object by an electronic device having a touch screen. The method includes recognizing at least two first touch inputs through the touch screen, recognizing transitions of the at least two first touch inputs to adjacent inputs that move adjacent to each other, and moving an object displayed on the touch screen in response to movements of the adjacent inputs.
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9.发明授权
公开(公告)号：US12195657B2
公开(公告)日：2025-01-14
申请号：US17687543
申请日：2022-03-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jooyeon Ahn , Taekhoon Kim , Deuk Kyu Moon , Jongmin Lee , Mi Hye Lim , Shin Ae Jun , Minho Kim , Yebin Jung
IPC: G02F1/13357 , C09D11/037 , C09D11/50 , C09K11/08 , C09K11/88 , G02F1/1335 , B82Y20/00 , B82Y40/00
Abstract: A color conversion panel that includes a color conversion layer including one or more color conversion regions, and optionally, a partition wall defining the regions of the color conversion layer, and a display device including the same. The color conversion region includes a first region corresponding to a first pixel, and the first region includes a first composite including a matrix and a plurality of luminescent nanostructures dispersed in the matrix. The luminescent nanostructures include a first semiconductor nanocrystal including a Group III-V compound and a second semiconductor nanocrystal including a zinc chalcogenide. The Group III-V compound includes indium, phosphorus, and optionally, zinc or gallium, or zinc and gallium, and the zinc chalcogenide includes zinc, selenium, and sulfur. The luminescent nanostructures do not include cadmium. The luminescent nanostructures further include fluorine, and in the luminescent nanostructures, a mole ratio of fluorine to indium is greater than or equal to about 0.05:1.
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公开(公告)号：US20240405014A1
公开(公告)日：2024-12-05
申请号：US18405843
申请日：2024-01-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jongkyu Song , Jin Heo , Minho Kim , Jooyoung Song , Eunsuk Lee , Chanhee Jeon
IPC: H01L27/02 , H01L27/06 , H01L29/06 , H01L29/735 , H01L29/78
Abstract: The present disclosure relates to semiconductor devices. An example semiconductor device includes a first well region and a second well region isolated from each other by a first device isolation film; an NPN transistor provided by a first collector region formed in the first well region and including first conductivity-type impurities, and a first emitter region formed in the second well region and including the first conductivity-type impurities; a PNP transistor provided by a second emitter region formed in the first well region and including second conductivity-type impurities different from the first conductivity-type, and a second collector region formed in the second well region and including the second conductivity-type impurities; and an NMOS transistor including a source region and a drain region formed in the second well region and including the first conductivity-type impurities, and a gate structure disposed between the source region and the drain region.
