公开(公告)号：USRE49375E1

公开(公告)日：2023-01-17

申请号：US17129109

申请日：2020-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myeong-cheol Kim ,  Cheol Kim ,  Jaehun Seo ,  YooJung Lee ,  Kisoo Chang ,  Siyoung Choi

IPC: H01L29/78 ,  H01L29/66

Abstract: Field effect transistors including a source region and a drain region on a substrate, a fin base protruding from a top surface of the substrate, a plurality of fin portions extending upward from the fin base and connecting the source region with the drain region, a gate electrode on the fin portions, and a gate dielectric between the fin portions and the gate electrode may be provided. A top surface of the substrate may include a plurality of grooves (e.g., a plurality of convex portions and a plurality of concave portions). Further, a device isolation layer may be provided to expose upper portions of the plurality of fin portions and to cover top surfaces of the plurality of grooves.

公开(公告)号：US20150104947A1

公开(公告)日：2015-04-16

申请号：US14510331

申请日：2014-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongchan Kim ,  Gyungjin Min ,  Minjoon Park ,  Seunghoon Park ,  KeunHee Bai ,  Kisoo Chang

IPC: H01L21/308 ,  H01L21/306

CPC classification number: H01L21/31111 ,  H01L21/31122 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/32139 ,  H01L29/66545 ,  H01L29/66795

Abstract: Methods of forming a semiconductor device are provided. The methods may include forming an insulating layer including silicon on a substrate and sequentially forming a first hard mask layer and a second hard mask layer on the substrate. The first hard mask layer may include carbon, and the second hard mask layer may include carbon and impurities. The first and second hard mask layers may expose at least a portion of the insulating layer. The methods may also include performing an etching process to selectively remove the second hard mask layer with respect to the insulating layer. A ratio of etch rates between the second hard mask layer and the insulating layer during the etching process may be in a range of about 100:1 to about 10,000:1.

Abstract translation: 提供了形成半导体器件的方法。 所述方法可以包括在衬底上形成包括硅的绝缘层，并且在衬底上依次形成第一硬掩模层和第二硬掩模层。 第一硬掩模层可以包括碳，第二硬掩模层可以包括碳和杂质。 第一和第二硬掩模层可以暴露绝缘层的至少一部分。 所述方法还可以包括执行蚀刻工艺以相对于绝缘层选择性地去除第二硬掩模层。 在蚀刻过程中，第二硬掩模层和绝缘层之间的蚀刻速率的比可以在约100:1至约10,000:1的范围内。

公开(公告)号：US08987836B2

公开(公告)日：2015-03-24

申请号：US13780855

申请日：2013-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-cheol Kim ,  Cheol Kim ,  Jaehun Seo ,  YooJung Lee ,  Kisoo Chang ,  Siyoung Choi

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L29/7851

Abstract: Field effect transistors including a source region and a drain region on a substrate, a fin base protruding from a top surface of the substrate, a plurality of fin portions extending upward from the fin base and connecting the source region with the drain region, a gate electrode on the fin portions, and a gate dielectric between the fin portions and the gate electrode may be provided. A top surface of the substrate may include a plurality of grooves (e.g., a plurality of convex portions and a plurality of concave portions). Further, a device isolation layer may be provided to expose upper portions of the plurality of fin portions and to cover top surfaces of the plurality of grooves.

Abstract translation: 场效应晶体管，其包括基板上的源极区域和漏极区域，从基板的顶面突出的翅片基板，从翅片基部向上延伸并将源极区域与漏极区域连接的多个翅片部， 翅片部分上的电极，以及翅片部分和栅电极之间的栅极电介质。 基板的顶面可以包括多个凹槽（例如，多个凸部和多个凹部）。 此外，可以设置器件隔离层以暴露多个翅片部分的上部并覆盖多个凹槽的顶表面。

公开(公告)号：US09859163B2

公开(公告)日：2018-01-02

申请号：US15235175

申请日：2016-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyounghoon Han ,  Junho Yoon ,  Kisoo Chang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/311 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/31144 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for manufacturing a semiconductor device includes forming gate structures spaced apart from each other on a substrate, gate spacers covering sidewalls of the gate structures, and an interlayer insulating layer covering the gate spacers, forming a contact hole that penetrates the interlayer insulating layer to expose a sidewall of at least one of the gate spacers, forming a sacrificial gap-fill pattern filling a lower portion of the contact hole, forming a contact spacer on a sidewall of the contact hole having the sacrificial gap-fill pattern, and forming a contact filling the contact hole after removing the sacrificial gap-fill pattern.

公开(公告)号：US09305802B2

公开(公告)日：2016-04-05

申请号：US14510331

申请日：2014-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongchan Kim ,  Gyungjin Min ,  Minjoon Park ,  Seunghoon Park ,  KeunHee Bai ,  Kisoo Chang

IPC: H01L21/31 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/31111 ,  H01L21/31122 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/32139 ,  H01L29/66545 ,  H01L29/66795

Abstract: Methods of forming a semiconductor device are provided. The methods may include forming an insulating layer including silicon on a substrate and sequentially forming a first hard mask layer and a second hard mask layer on the substrate. The first hard mask layer may include carbon, and the second hard mask layer may include carbon and impurities. The first and second hard mask layers may expose at least a portion of the insulating layer. The methods may also include performing an etching process to selectively remove the second hard mask layer with respect to the insulating layer. A ratio of etch rates between the second hard mask layer and the insulating layer during the etching process may be in a range of about 100:1 to about 10,000:1.

Abstract translation: 提供了形成半导体器件的方法。 所述方法可以包括在衬底上形成包括硅的绝缘层，并且在衬底上依次形成第一硬掩模层和第二硬掩模层。 第一硬掩模层可以包括碳，第二硬掩模层可以包括碳和杂质。 第一和第二硬掩模层可以暴露绝缘层的至少一部分。 所述方法还可以包括执行蚀刻工艺以相对于绝缘层选择性地去除第二硬掩模层。 在蚀刻过程中，第二硬掩模层和绝缘层之间的蚀刻速率的比可以在约100:1至约10,000:1的范围内。