公开(公告)号：US20240373621A1

公开(公告)日：2024-11-07

申请号：US18627685

申请日：2024-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin SHIN ,  Kijong PARK ,  Sangjun PARK ,  Younggeun SONG ,  Ilyoung YOON ,  Yongjin LEE

IPC: H10B12/00

Abstract: In a method for manufacturing a semiconductor device, comprising; forming mold insulation patterns on a substrate, forming an oxide semiconductor layer conformally on sidewalls and upper surfaces of the mold insulation patterns and the substrate, forming a first metal oxide layer on the oxide semiconductor layer, patterning the first sacrificial layer, the first metal oxide layer, and the oxide semiconductor layer to form a first structure including a preliminary first metal oxide layer pattern, a preliminary oxide semiconductor layer pattern and a first sacrificial layer pattern stacked, forming a preliminary second metal oxide layer pattern selectively on a sidewall of the preliminary oxide semiconductor layer pattern, removing selective portions of the first structure and the preliminary second metal oxide layer pattern to form an oxide semiconductor layer pattern, a first metal oxide layer pattern, and a second metal oxide layer pattern.

公开(公告)号：US20240014068A1

公开(公告)日：2024-01-11

申请号：US18217724

申请日：2023-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yanghee LEE ,  Byoungho KWON ,  Jonghyuk PARK ,  Boun YOON ,  Ilyoung YOON ,  Seokjun HONG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H10B12/00

CPC classification number: H01L21/76832 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53266 ,  H01L23/53238 ,  H01L21/76816 ,  H01L23/53295 ,  H10B12/315

Abstract: A semiconductor device includes a lower structure; an intermediate insulating structure on the lower structure; an intermediate interconnection structure penetrating through the intermediate insulating structure; an upper insulating structure on the intermediate insulating structure and the intermediate interconnection structure; and an upper conductive pattern penetrating through the upper insulating structure and electrically connected to the intermediate interconnection structure, wherein the intermediate insulating structure includes an intermediate etch-stop layer and an intermediate insulating layer thereon, the intermediate insulating layer includes first and second intermediate material layers, the second intermediate material layer having an upper surface coplanar with an upper surface of the first intermediate material layer, the intermediate interconnection structure penetrates through the first intermediate material layer and the intermediate etch-stop layer, and a material of the first intermediate material layer has a dielectric constant that is higher than a dielectric constant of a material of the second intermediate material layer.

公开(公告)号：US20140227848A1

公开(公告)日：2014-08-14

申请号：US14146185

申请日：2014-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bo Kyeong KANG ,  Jaeseok KIM ,  Boun YOON ,  Hoyoung KIM ,  Ilyoung YOON

IPC: H01L21/8234

CPC classification number: H01L21/823431 ,  H01L21/823456 ,  H01L21/823481

Abstract: A method of fabricating a semiconductor device includes forming first gate patterns on a semiconductor substrate using an etch mask pattern, forming a trench in the semiconductor substrate between the first gate patterns, forming an insulating layer in the trench, such that the insulating layer fills the trench and is disposed on the etch mask pattern, planarizing the insulating layer until a top surface of the etch mask pattern is exposed, etching a portion of the planarized insulating layer to form a device isolation layer in the trench, forming a second gate layer covering the etch mask pattern and disposed on the device isolation pattern, and planarizing the second gate layer until the top surface of the etch mask pattern is exposed, such that a second gate pattern is formed.

Abstract translation: 制造半导体器件的方法包括使用蚀刻掩模图案在半导体衬底上形成第一栅极图案，在第一栅极图案之间的半导体衬底中形成沟槽，在沟槽中形成绝缘层，使得绝缘层填充 沟槽，并且设置在蚀刻掩模图案上，使绝缘层平坦化，直到暴露蚀刻掩模图案的顶表面，蚀刻平坦化绝缘层的一部分以在沟槽中形成器件隔离层，形成第二栅极层覆盖层 蚀刻掩模图案并且设置在器件隔离图案上，并且平坦化第二栅极层，直到暴露出蚀刻掩模图案的顶表面，使得形成第二栅极图案。

公开(公告)号：US20230253241A1

公开(公告)日：2023-08-10

申请号：US17965927

申请日：2022-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youncheol JEONG ,  Jaeung KOO ,  Boun YOON ,  Ilyoung YOON

IPC: H01L21/762 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8238

CPC classification number: H01L21/76232 ,  H01L27/0924 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/823878 ,  H01L29/7851

Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode extending in a second direction and crossing the active pattern, a gate capping pattern covering a top surface of the gate electrode, and a separation structure at a side of the gate electrode and extending in the second direction to penetrate the active pattern in a third direction. The first and second directions are parallel to a bottom surface of the substrate and are perpendicular to the third direction. The separation structure may include a filling pattern, which extends in the third direction to penetrate the active pattern, and a vertical insulating pattern, which is interposed between the filling pattern and the gate electrode. A top surface of the separation structure may be located at a height lower than a top surface of the gate capping pattern.

公开(公告)号：US20230005935A1

公开(公告)日：2023-01-05

申请号：US17713327

申请日：2022-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanghee LEE ,  Jonghyuk PARK ,  Ilyoung YOON ,  Boun YOON ,  Jeehwan HEO

IPC: H01L27/108

Abstract: A semiconductor device may include a substrate, a patterned structure, a filling pattern, and a conductive spacer. The substrate may include a semiconductor chip region and an overlay region. The patterned structure may include bit line structures spaced by a first distance on the semiconductor region, define a first trench and a second trench on first and second regions of the overlay region, and include key structures on the second region and spaced apart by the second trench. The filling pattern may fill lower portions of the first and second trenches on the first and second regions. The first region may be an edge portion of the overlay region. The second region may be a central portion of the overlay region. The conductive spacer may contact an upper surface of the filling pattern and may be on an upper sidewall of each of the first and second trenches.

公开(公告)号：US20240147697A1

公开(公告)日：2024-05-02

申请号：US18308376

申请日：2023-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yanghee LEE ,  Byoungho KWON ,  Seongeun KIM ,  Sujeong KIM ,  Jonghyuk PARK ,  Ilyoung YOON ,  Woohyuk JANG ,  Byungsoo JOO

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/09 ,  H10B12/482

Abstract: A semiconductor device includes a substrate, a chip region in the substrate, a scribe lane region in the substrate, first active patterns in the chip region, a first device isolation pattern on the first active patterns, second active patterns in the scribe lane region, and a second device isolation pattern on the second active patterns. The scribe lane region is adjacent to the chip region. The first device isolation pattern includes a first device isolation material, and the second device isolation pattern includes a second device isolation material. The second device isolation material is different from the first device isolation material.

公开(公告)号：US20220069101A1

公开(公告)日：2022-03-03

申请号：US17196321

申请日：2021-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghoon CHOI ,  Ilyoung YOON ,  Ilsu PARK ,  Kiho BAE ,  Boun YOON ,  Yooyong LEE

IPC: H01L29/49 ,  H01L29/423 ,  H01L21/8234

Abstract: A semiconductor device including a substrate; a gate structure on the substrate; a gate spacer on a sidewall of the gate structure; and a polishing stop pattern on the gate structure and the gate spacer, the polishing stop pattern including a first portion covering an upper surface of the gate structure and an upper surface of the gate spacer; and a second portion extending from the first portion in a vertical direction substantially perpendicular to an upper surface of the substrate, wherein an upper surface of a central portion of the first portion of the polishing stop pattern is higher than an upper surface of an edge portion of the first portion thereof, and the upper surface of the central portion of the first portion of the polishing stop pattern is substantially coplanar with an upper surface of the second portion thereof.