公开(公告)号：US20190205252A1

公开(公告)日：2019-07-04

申请号：US15858787

申请日：2017-12-29

Applicant: Oracle International Corporation

Inventor： PAUL N. LOEWENSTEIN ,  DAMIEN WALKER ,  PRIYAMBADA MITRA ,  ALI VAHIDSAFA ,  MATTHEW COHEN ,  JOSEPHUS EBERGEN ,  ANDREW BROCK

IPC: G06F12/0817 ,  G06F12/128 ,  G06F12/0813

CPC classification number: G06F12/0824 ,  G06F12/0813 ,  G06F12/0828 ,  G06F12/128 ,  G06F2212/621

Abstract: A cache coherence system manages both internode and intranode cache coherence in a cluster of nodes. Each node in the cluster of nodes is either a collection of processors running an intranode coherence protocol between themselves, or a single processor. A node comprises a plurality of coherence ordering units (COUs) that are hardware circuits configured to manage intranode coherence of caches within the node and/or internode coherence with caches on other nodes in the cluster. Each node contains one or more directories which tracks the state of cache line entries managed by the particular node. Each node may also contain one or more scoreboards for managing the status of ongoing transactions. The internode cache coherence protocol implemented in the COUs may be used to detect and resolve communications errors, such as dropped message packets between nodes, late message delivery at a node, or node failure. Additionally, a transport layer manages communication between the nodes in the cluster, and can additionally be used to detect and resolve communications errors.

公开(公告)号：US20190207714A1

公开(公告)日：2019-07-04

申请号：US15859037

申请日：2017-12-29

Applicant: Oracle International Corporation

Inventor： PAUL N. LOEWENSTEIN ,  DAMIEN WALKER ,  PRIYAMBADA MITRA ,  ALI VAHIDSAFA ,  MATTHEW COHEN ,  JOSEPHUS EBERGEN ,  ANDREW BROCK

IPC: H04L1/08 ,  G06F12/0813 ,  G06F12/0842

CPC classification number: G06F12/0828 ,  G06F12/0813 ,  G06F12/0842 ,  G06F2212/1032 ,  G06F2212/154 ,  G06F2212/60 ,  G06F2212/62

Abstract: A cache coherence system manages both internode and intranode cache coherence in a cluster of nodes. Each node in the cluster of nodes is either a collection of processors running an intranode coherence protocol between themselves, or a single processor. A node comprises a plurality of coherence ordering units (COUs) that are hardware circuits configured to manage intranode coherence of caches within the node and/or internode coherence with caches on other nodes in the cluster. Each node contains one or more directories which tracks the state of cache line entries managed by the particular node. Each node may also contain one or more scoreboards for managing the status of ongoing transactions. The internode cache coherence protocol implemented in the COUs may be used to detect and resolve communications errors, such as dropped message packets between nodes, late message delivery at a node, or node failure. Additionally, a transport layer manages communication between the nodes in the cluster, and can additionally be used to detect and resolve communications errors.