Reduced cross-talk pixel-array substrate and fabrication method

    公开(公告)号:US11695030B2

    公开(公告)日:2023-07-04

    申请号:US17138711

    申请日:2020-12-30

    Inventor: Seong Yeol Mun

    Abstract: A pixel-array substrate includes a semiconductor substrate, a buffer layer, and a metal annulus. The semiconductor substrate includes a first-photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the first-photodiode region in a cross-sectional plane parallel to a first back-surface region of the back surface above the first-photodiode region. The buffer layer is on the back surface and has (i) a thin buffer-layer region located above the first-photodiode region and (ii) a thick buffer-layer region forming an annulus above the trench in a plane parallel to the cross-sectional plane. The metal annulus is on the buffer layer and covers the thick buffer-layer region.

    METAL GRID STRUCTURE INTEGRATED WITH DEEP TRENCH ISOLATION STRUCTURE

    公开(公告)号:US20220320163A1

    公开(公告)日:2022-10-06

    申请号:US17217937

    申请日:2021-03-30

    Abstract: A high k passivation layer, an anti-reflective coating layer, and a buffer layer are disposed over semiconductor substrate including photodiodes formed therein. Trenches are etched into the semiconductor substrate through the buffer layer, anti-reflective coating layer, and the high k passivation layer in a grid-like pattern surrounding each of the photodiodes in the semiconductor substrate. Another high k passivation layer lines an interior of the trenches in the semiconductor substrate. An adhesive and barrier layer is deposited over the high k passivation layer that lines the interior of the trenches. A deep trench isolation (DTI) structure is formed with conductive material deposited into the trenches over the adhesive and barrier layer to fill the trenches. A grid structure is formed over the DTI structure and above a plane of the buffer layer. The grid structure is formed with the conductive material.

    Image sensor with split pixel structure and method of manufacturing thereof

    公开(公告)号:US11217613B2

    公开(公告)日:2022-01-04

    申请号:US16687660

    申请日:2019-11-18

    Abstract: An image sensor includes a substrate material. The substrate material includes a plurality of photodiodes disposed therein. The plurality of photodiodes includes a plurality of small photodiodes (SPDs) and a plurality of large photodiodes (LPDs) larger than the SPDs. An array of color filters is disposed over the substrate material. A buffer layer is disposed between the substrate material and the array of color filters. A metal pattern is disposed between the color filters in the array of color filters, and between the array of color filters and the buffer layer. An attenuation layer is disposed between the substrate material and the array of color filters. The attenuation layer is above and aligned with the plurality of SPDs and a portion of each of the plurality of LPDs. An edge of the attenuation layer is over one of the plurality of LPDs.

    Method of forming shallow trench isolation (STI) structure for suppressing dark current

    公开(公告)号:US11705475B2

    公开(公告)日:2023-07-18

    申请号:US17558858

    申请日:2021-12-22

    Inventor: Seong Yeol Mun

    Abstract: A method of fabricating a target shallow trench isolation (STI) structure between devices in a wafer-level image sensor having a large number of pixels includes etching a trench, the trench having a greater depth and width than a target STI structure and epitaxially growing the substrate material in the trench for a length of time necessary to provide the target depth and width of the isolation structure. An STI structure formed in a semiconductor substrate includes a trench etched in the substrate having a depth and width greater than that of the STI structure, and semiconductor material epitaxially grown in the trench to provide a critical dimension and target depth of the STI structure. An image sensor includes a semiconductor substrate, a photodiode region, a pixel transistor region and an STI structure between the photodiode region and the pixel transistor region.

    High dynamic range split pixel CMOS image sensor with low color crosstalk

    公开(公告)号:US11527569B2

    公开(公告)日:2022-12-13

    申请号:US16877077

    申请日:2020-05-18

    Abstract: A pixel cell includes a plurality of subpixels to generate image charge in response to incident light. The subpixels include an inner subpixel laterally surrounded by outer subpixels. A first plurality of transfer gates disposed proximate to the inner subpixel and a first grouping of outer subpixels. A first floating diffusion is coupled to receive the image charge from the first grouping of outer subpixels through a first plurality of transfer gates. A second plurality of transfer gates disposed proximate to the inner subpixel and the second grouping of outer subpixels. A second floating diffusion disposed in the semiconductor material and coupled to receive the image charge from each one of the second grouping of outer subpixels through the second plurality of transfer gates. The image charge in the inner subpixel is received by the first, second, or both floating diffusions through respective transfer gates.

    TRANSISTOR HAVING INCREASED EFFECTIVE CHANNEL WIDTH

    公开(公告)号:US20220246656A1

    公开(公告)日:2022-08-04

    申请号:US17727247

    申请日:2022-04-22

    Abstract: Methods of forming transistors include providing a substrate material, forming a recess to a first depth in the substrate material, the recess corresponding to a gate region and extending in a channel length direction and a channel width direction that is perpendicular to the channel length direction, forming a trench structure in the substrate material by deepening the recess to a second depth using an isotropic process, forming an isolation layer on the substrate material, forming a gate portion of the isolation layer on the substrate material such that the gate portion of the isolation layer extends into the trench structure, and forming a gate on the isolation layer such that the gate extends into the trench structure.

    ISOLATION STRUCTURE FOR SUPPRESSION FLOATING DIFFUSION JUNCTION LEAKAGE IN CMOS IMAGE SENSOR

    公开(公告)号:US20220013554A1

    公开(公告)日:2022-01-13

    申请号:US16946839

    申请日:2020-07-08

    Abstract: Examples of the disclosed subject matter propose disposing deep trench isolation structure around the perimeter of the pixel transistor region of the pixel cell. In some example embodiments, the deep trench isolation structure extends into the semiconductor substrate from the back side of the semiconductor substrate and abuts against or contacts the bottom of shallow trench isolation structure disposed in the front side of the semiconductor substrate. Together, the trench isolating structure isolates the transistor channel of the pixel transistor region. The formation and arrangement of the trench isolation structure in the pixel transistor region forms a floating doped well region, such as a floating P-doped well region (P-well), containing a floating diffusion (FD) and source/drains (e.g., (N) doped regions) of the pixel transistors. This floating P-well region aims to reduce junction leakage associated with the floating diffusion region of the pixel cell.

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