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公开(公告)号:US11695030B2
公开(公告)日:2023-07-04
申请号:US17138711
申请日:2020-12-30
Applicant: OmniVision Technologies, Inc.
Inventor: Seong Yeol Mun
IPC: H01L27/146
CPC classification number: H01L27/14647 , H01L27/14621 , H01L27/14627 , H01L27/14683
Abstract: A pixel-array substrate includes a semiconductor substrate, a buffer layer, and a metal annulus. The semiconductor substrate includes a first-photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the first-photodiode region in a cross-sectional plane parallel to a first back-surface region of the back surface above the first-photodiode region. The buffer layer is on the back surface and has (i) a thin buffer-layer region located above the first-photodiode region and (ii) a thick buffer-layer region forming an annulus above the trench in a plane parallel to the cross-sectional plane. The metal annulus is on the buffer layer and covers the thick buffer-layer region.
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公开(公告)号:US20220320163A1
公开(公告)日:2022-10-06
申请号:US17217937
申请日:2021-03-30
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor: Seong Yeol Mun , Yibo Zhu , Keiji Mabuchi
IPC: H01L27/146
Abstract: A high k passivation layer, an anti-reflective coating layer, and a buffer layer are disposed over semiconductor substrate including photodiodes formed therein. Trenches are etched into the semiconductor substrate through the buffer layer, anti-reflective coating layer, and the high k passivation layer in a grid-like pattern surrounding each of the photodiodes in the semiconductor substrate. Another high k passivation layer lines an interior of the trenches in the semiconductor substrate. An adhesive and barrier layer is deposited over the high k passivation layer that lines the interior of the trenches. A deep trench isolation (DTI) structure is formed with conductive material deposited into the trenches over the adhesive and barrier layer to fill the trenches. A grid structure is formed over the DTI structure and above a plane of the buffer layer. The grid structure is formed with the conductive material.
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公开(公告)号:US11217613B2
公开(公告)日:2022-01-04
申请号:US16687660
申请日:2019-11-18
Applicant: OmniVision Technologies, Inc.
Inventor: Bill Phan , Yuanliang Liu , Duli Mao , Seong Yeol Mun , Alireza Bonakdar
IPC: H01L27/146 , H04N5/378
Abstract: An image sensor includes a substrate material. The substrate material includes a plurality of photodiodes disposed therein. The plurality of photodiodes includes a plurality of small photodiodes (SPDs) and a plurality of large photodiodes (LPDs) larger than the SPDs. An array of color filters is disposed over the substrate material. A buffer layer is disposed between the substrate material and the array of color filters. A metal pattern is disposed between the color filters in the array of color filters, and between the array of color filters and the buffer layer. An attenuation layer is disposed between the substrate material and the array of color filters. The attenuation layer is above and aligned with the plurality of SPDs and a portion of each of the plurality of LPDs. An edge of the attenuation layer is over one of the plurality of LPDs.
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公开(公告)号:US20240105755A1
公开(公告)日:2024-03-28
申请号:US18527841
申请日:2023-12-04
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor: Heesoo Kang , Bill Phan , Seong Yeol Mun
IPC: H01L27/146
CPC classification number: H01L27/14647 , H01L27/14607 , H01L27/14621 , H01L27/14627 , H01L27/1463 , H01L27/14685 , H01L27/14689
Abstract: SiGe photodiode for crosstalk reduction. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array disposed in a semiconductor material. Each pixel includes a plurality of photodiodes. The plurality of pixels are configured to receive an incoming light through an illuminated surface of the semiconductor material. Each pixel includes a first photodiode comprising a silicon (Si) material; and a second photodiode having the Si material and a silicon germanium (SiGe) material.
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公开(公告)号:US11901383B2
公开(公告)日:2024-02-13
申请号:US17727247
申请日:2022-04-22
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor: Seong Yeol Mun , Young Woo Jung
IPC: H01L27/146 , H01L29/786 , H01L21/8238 , H01L29/423 , H01L21/8234
CPC classification number: H01L27/14616 , H01L27/1463 , H01L27/14614 , H01L27/14636 , H01L27/14643 , H01L27/14683 , H01L21/823412 , H01L21/823807 , H01L29/4236 , H01L29/78642
Abstract: Methods of forming transistors include providing a substrate material, forming a recess to a first depth in the substrate material, the recess corresponding to a gate region and extending in a channel length direction and a channel width direction that is perpendicular to the channel length direction, forming a trench structure in the substrate material by deepening the recess to a second depth using an isotropic process, forming an isolation layer on the substrate material, forming a gate portion of the isolation layer on the substrate material such that the gate portion of the isolation layer extends into the trench structure, and forming a gate on the isolation layer such that the gate extends into the trench structure.
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公开(公告)号:US11705475B2
公开(公告)日:2023-07-18
申请号:US17558858
申请日:2021-12-22
Applicant: OmniVision Technologies, Inc.
Inventor: Seong Yeol Mun
IPC: H01L27/146
CPC classification number: H01L27/14687 , H01L27/1463 , H01L27/14603 , H01L27/14632 , H01L27/14689
Abstract: A method of fabricating a target shallow trench isolation (STI) structure between devices in a wafer-level image sensor having a large number of pixels includes etching a trench, the trench having a greater depth and width than a target STI structure and epitaxially growing the substrate material in the trench for a length of time necessary to provide the target depth and width of the isolation structure. An STI structure formed in a semiconductor substrate includes a trench etched in the substrate having a depth and width greater than that of the STI structure, and semiconductor material epitaxially grown in the trench to provide a critical dimension and target depth of the STI structure. An image sensor includes a semiconductor substrate, a photodiode region, a pixel transistor region and an STI structure between the photodiode region and the pixel transistor region.
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公开(公告)号:US11647300B2
公开(公告)日:2023-05-09
申请号:US17247321
申请日:2020-12-07
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor: Seong Yeol Mun
IPC: H04N25/57 , H01L27/146 , H04N25/702 , H04N25/76 , H04N25/13 , H04N25/585 , H04N25/77
CPC classification number: H04N25/57 , H01L27/14603 , H01L27/14643 , H01L27/14683 , H04N25/702 , H04N25/76
Abstract: A pixel array for a high definition (HD) image sensor is disclosed. The pixel array includes a number of split pixel cells each including a first photodiode and a second photodiode that is more sensitive to incident light than the first photodiode. The first photodiode can be used to sense bright or high intensity light conditions, while the second photodiode can be used to sense low to medium intensity light conditions. In the disclosed pixel array, the sensitivity of one or more photodiodes is reduced by application of a light attenuation layer over the first photodiode of each split pixel cell. In accordance with methods of the disclosure, the light attenuation layer can be formed prior to the formation of a metal, optical isolation grid structure. This can lead to better control of the thickness and uniformity of light attenuation layer.
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公开(公告)号:US11527569B2
公开(公告)日:2022-12-13
申请号:US16877077
申请日:2020-05-18
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor: Duli Mao , Bill Phan , Keiji Mabuchi , Seong Yeol Mun , Yuanliang Liu , Vincent Venezia
IPC: H01L27/146 , H04N5/378
Abstract: A pixel cell includes a plurality of subpixels to generate image charge in response to incident light. The subpixels include an inner subpixel laterally surrounded by outer subpixels. A first plurality of transfer gates disposed proximate to the inner subpixel and a first grouping of outer subpixels. A first floating diffusion is coupled to receive the image charge from the first grouping of outer subpixels through a first plurality of transfer gates. A second plurality of transfer gates disposed proximate to the inner subpixel and the second grouping of outer subpixels. A second floating diffusion disposed in the semiconductor material and coupled to receive the image charge from each one of the second grouping of outer subpixels through the second plurality of transfer gates. The image charge in the inner subpixel is received by the first, second, or both floating diffusions through respective transfer gates.
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公开(公告)号:US20220246656A1
公开(公告)日:2022-08-04
申请号:US17727247
申请日:2022-04-22
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor: Seong Yeol Mun , Young Woo Jung
IPC: H01L27/146
Abstract: Methods of forming transistors include providing a substrate material, forming a recess to a first depth in the substrate material, the recess corresponding to a gate region and extending in a channel length direction and a channel width direction that is perpendicular to the channel length direction, forming a trench structure in the substrate material by deepening the recess to a second depth using an isotropic process, forming an isolation layer on the substrate material, forming a gate portion of the isolation layer on the substrate material such that the gate portion of the isolation layer extends into the trench structure, and forming a gate on the isolation layer such that the gate extends into the trench structure.
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10.
公开(公告)号:US20220013554A1
公开(公告)日:2022-01-13
申请号:US16946839
申请日:2020-07-08
Applicant: OmniVision Technologies, Inc.
Inventor: Seong Yeol Mun , Bill Phan
IPC: H01L27/146
Abstract: Examples of the disclosed subject matter propose disposing deep trench isolation structure around the perimeter of the pixel transistor region of the pixel cell. In some example embodiments, the deep trench isolation structure extends into the semiconductor substrate from the back side of the semiconductor substrate and abuts against or contacts the bottom of shallow trench isolation structure disposed in the front side of the semiconductor substrate. Together, the trench isolating structure isolates the transistor channel of the pixel transistor region. The formation and arrangement of the trench isolation structure in the pixel transistor region forms a floating doped well region, such as a floating P-doped well region (P-well), containing a floating diffusion (FD) and source/drains (e.g., (N) doped regions) of the pixel transistors. This floating P-well region aims to reduce junction leakage associated with the floating diffusion region of the pixel cell.